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ID	Date	Author	Category	Subject
1	Wed Jun 15 13:11:38 2022	Guy Leckenby	DAQ	Signal Diagram
Attached is the signal mapping that will be used for the BEAVERTAIL test. Note we plan to use 5 FEBEX cards to run 8 Si detectors because we will only use one pocket setup this time. In future, a solution using only 4 FEBEX cards will need to be found.
Attachment 1: Beavertail_Signal_Map.pdf

2	Fri Jun 17 15:32:47 2022	Guy Leckenby	Electronics	Preamp Settings
Bias Select: In general, higher bias resistors -> lower electronic noise. However, higher resistance = larger voltage drop due to leakage current. Our natural leakage currents at operating voltage of 60V range from 18nA (MSPad 15A) to 320nA (Design I 13). At maximum expected rate of 100Hz, our signal induced leakage current is 8.9nA. Hence our voltage drop range is 0.54V to 6.6V with 20MOhm resistors. Since we are not electronically noise limited with GeV signals, we decided to choose the lower resistance in case any detectors have bad leakage currents to ensure a good comparison. For Silicon detectors: p-side collects positive signals, n-side collects negative signals. Finally, the expected signal energy for each detector is: - 1st Si pad -> 2.2GeV - 7th Si pad -> 2.5GeV - CsI scint -> 1.3GeV - GAGG scint -> 0.9GeV - BGO scint -> 129MeV As a result, all Si preamps were set to 5GeV max range (MSI#1 Ch1-8 & MSI#2 Ch1-4). CsI & GAGG will use 4GeV range preamps (MSI#2 Ch7-8). BGO will use 330MeV preamps (MSI#2 Ch5-6). Attached is the final MSI-8 preamp setup using the above settings.
Attachment 1: Preamp_Settings.png

3	Mon Jun 20 10:36:56 2022	Guy Leckenby	DAQ	DAQ Startup Commands
Three terminals/processes are required to record data on a local machine. 1. log in x86l-131. cd to '2021-beavertail/febex3-x86l-131' 'resl' to clear, then run 'mbs' '@startup' -> initialises mbs by running startup script, 'show acq' gets status, check if there are triggers incoming 2. new terminal on lab machine, cd to /data.local2/2022_beavertail to record data, run ./rawDispRFIO64-wheezy, then data record is listening bacl to mbs terminal, to send data, '@connect.scom' -> this a a connection script to connect mbs to RFIO @openfile.scom -> opens data file to record and automatically names them run####.lmd. @closefile.scom -> closes file and stops file writing 'show file' show connection to file, and whether its open/closed 'type event' shows header, 1 words = related to data readout. -v shows full event output. 3. monitor with go4 cd ~/beavertail/go4/CsISiPHOS_febex/ source /u/litv-exp/go4login go4 x86l-131.hotstart Our DAQ machines are x86l-131 (DAQ-1), x86l-124 (DAQ-2), x86l-128 (Time-sorter) litv-exp has /beavertail folder for our testing. x86l- DAQ computers have remote folder kept somewhere. These will run. To login remotely: Log into lx-pool.gsi.de with litv-exp user: ssh -XY litv-exp@lx-pool.gsi.de From lx-pool you need another tunnel: ssh lxg1050 From there (or any other lxg-machine) you can do: ssh x86l-131
4	Tue Jun 21 02:37:07 2022	Guy Leckenby, Iris Dillmann, Chris Griffin	General	Run notes
Beam: 208Pb(82+), 269.0 MeV/u, ~210^7 ions in ESR Position pocket outside: GE01DD2AG (A= aussen, outside) Position -126mm outside (very left), beam at ~-15mm - BGO runs electron cooler current: 20 mA (at ~2:00 am) (SC06): Moved pocket to -20mm run005-033 with traces on. runs034-037 no traces rate is 1.2kHz At ~2:35am (run038) changed e current to 100 mA, rate increase to 3kHz.: run038-080(?) no traces. run080-117 incl traces - GAGG runs ~610^6 ions Pocket at -20 mm, e current at 100 mA Moved pocket to -50mm, 200 mA e current run0114 - run0143 incl. traces run0149 - run0157 no traces -> moving detector in/out run0158 - run01?? cooler voltage changed from 100mA to 200mA - large CsI ~2*10^7 particles in ring 100 mA e current run0167 - run0197 incl. traces. Moved detector position from -70mm to -20mm in steps of 10mm run0??? - run0210 no traces. Status detector pocket.
Attachment 1: Pocket-drive.png

Attachment 2: ecooler-current.png

Attachment 3: 208Pb82_Beam-Lifetime.png

5	Wed Jun 22 18:01:18 2022	Guy Leckenby	Detectors	Detector Arrangment
Attached is the detector arrangement for the 3 setups used during the tests.
Attachment 1: Detector_Setups_for_Test.pdf

6	Wed Jun 22 19:14:12 2022	Guy Leckenby	DAQ	FBEX Script Choices
Here were the f_user.c choices we implemented for this experiment. Ln029: No white rabbit time stamp available so commented out. This needs to be done in the Go4 analysis script too. Ln087: We used SFP 1 (random port choice) with 5 FEBEX cards (see signal map) Ln104: We controlled traces. Ln163: Channel control: we used 0x91000000 (all enabled,etc) for positive signals, 0x81000000 for negative signals. Ln191: Sparsifying turned on for all channels. Ln217: Trigger enabled as OR of pads 2, 4, and 6 + PD front and back: 0xef00, 0x0000, 0x00ef, 0x00ef, 0xc02a. Ln257-261: Thresholds set to 0x85f as value that partially suppressed our pulser. Tbh, thresholds didn't seem to make an impact to our signal so we just left it at that.
Attachment 1: f_user.c
/* * Modified f_usr for the June 2022 pocket detector tests. * 1x pad detector, 1x 60x40 DSSD, 5x pad detctor, 1x scint+SiPD * * 1 DAQ computer * 1 FEBEX crate connected to SFP1 * 5 FEBEX cards in crate * 16 channels active on each card * * C. Griffin and G. Leckenby * * cgriffin@triumf.ca and gleckenby@triumf.ca * / // N.Kurz, EE, GSI, 3-Feb-2010 // N.Kurz, EE, GSI, 28-Oct-2020: USE_KINPEX_V5 activates new functions added to the kinpex firmware // version 5.0 by S.Minami. reduces number of accesses to KINPEX register // during token readout. // pexor febex triggered readout //---------------------------------------------------------------------------- // User change area: comment with // if #defines below shall be switched off //#define USE_MBSPEX_LIB 1 // this define will switch on usage of mbspex lib with locked ioctls // instead of direct register mapping usage //#define WR_TIME_STAMP 1 // white rabbit latched time stamp #define USE_KINPEX_V5 1 #define WRITE_ANALYSIS_PARAM 1 //#define LVDS_OUT 1 #define DEBUG 1 #ifdef WR_TIME_STAMP #define USE_TLU_FINE_TIME 1 //#define WR_USE_TLU_DIRECT 1 // N.Kurz, 29-Oct-2020: ist langsamer als etherbone readout ???!!! #endif //---------------------------------------------------------------------------- #include "stdio.h" #include "s_veshe.h" #include "stdarg.h" #include <sys/file.h> #ifndef Linux #include <mem.h> #include <smem.h> #else #include "smem_mbs.h" #include <unistd.h> #include <stdlib.h> #include <string.h> #include <sys/mman.h> #endif #include "sbs_def.h" #include "error_mac.h" #include "errnum_def.h" #include "err_mask_def.h" #include "f_ut_printm.h" #include "f_user_trig_clear.h" #include "./pexor_gosip.h" #ifdef USE_MBSPEX_LIB #include "mbspex/libmbspex.h" #endif #ifdef WR_TIME_STAMP #include <etherbone.h> #include <gsi_tm_latch.h> // wishbone devices #endif // WR_TIME_STAMP //---------------------------------------------------------------------------- // User change area: #define MAX_SFP 4 #define MAX_SLAVE 16 #define FEBEX_CH 16 // nr of slaves on SFP 0 1 2 3 // \| \| \| \| #define NR_SLAVES { 0, 5, 0, 0} //\/\/\/\/\/ DEFINE NUMBER OF CARDS USED IN FEBEX CRATE \/\/\/\/\/\// // maximum trace length 8000 (133 us) // attention // CVT to set: trace length - irq latency (10us) #define FEB_TRACE_LEN 3000 // in nr of samples #define FEB_TRIG_DELAY 200 // in nr.of samples //#define FEB_TRACE_LEN 200 // in nr of samples //#define FEB_TRIG_DELAY 100 // in nr.of samples //#define CLK_SOURCE_ID {0xff,0} // sfp_port, module_id of the module to distribute clock #define CLK_SOURCE_ID {0x0,0} // sfp_port, module_id of the module to distribute clock //-------------------------------------------------------------------------------------------------------- #define DATA_FILT_CONTROL_REG 0x2080C0 #define DATA_FILT_CONTROL_DAT 0x84 // (0x80 E,t summary always + data trace always (contingent on sparsifying) // (0x82 E,t summery always + (data trace + filter trace) always // (0x84 E,t summery always + data trace if > 1 hit (supercedes sparsifying for >1 hit) // (0x86 E,t summery always + (data trace + filter trace) if > 1 hit // Trigger/Hit finder filter #define TRIG_SUM_A_REG 0x2080D0 #define TRIG_GAP_REG 0x2080E0 #define TRIG_SUM_B_REG 0x2080F0 #define TRIG_SUM_A 8 // for 12 bit: 8, 4 ,9 (8+1); for 14 bit: 14, 4, 15 (14 + 1). #define TRIG_GAP 4 #define TRIG_SUM_B 9 // 8 + 1: one has to be added. // Energy Filters and Modes #define ENABLE_ENERGY_FILTER 1 #define TRAPEZ 1 // if TRAPEZ is off, MWD will be activated #ifdef ENABLE_ENERGY_FILTER #ifdef TRAPEZ #define ENERGY_SUM_A_REG 0x208090 #define ENERGY_GAP_REG 0x2080A0 #define ENERGY_SUM_B_REG 0x2080B0 #define ENERGY_SUM_A 15 #define ENERGY_GAP 5 #define ENERGY_SUM_B 16 // 64 + 1: one has to be added. #endif #endif //-------------------------------------------------------------------------------------------------------- // // bit 31 12 bit adc: 0 // 14 bit adc: 1 // // bit 28 signal polarity: 0: positive, <-- very important info for fpga hit finder! // 1: negative <-- " // bit 24 - 27 trigger methode: 0: 3step // 1: 2-window 60 MHz // 2: 2-window 30 MHz // 4: 2-window 15 MHz // 8: 2-window 7.5 MHz // bit 20 even-odd or 0: disabled // 1: enabled // bit 0 - 16 disable channels: bit 0: special channel, bit 1-16: adc channels // 0x00000: all enabled // 0x1fffe: all adc channels disabled, special channel enabled //-------------------------------------------------------------------------------------------------------- static long l_sfp0_feb_ctrl0[MAX_SLAVE] = { 0x01000000, 0x01000000, 0x01000000, 0x01000000, //Not used 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 }; static long l_sfp1_feb_ctrl0[MAX_SLAVE] = { 0x91000000, 0x91000000, 0x91000000, 0x91000000, 0x81000000, //Only first five used 0x91000000, 0x91000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000, 0x92000000 }; static long l_sfp2_feb_ctrl0[MAX_SLAVE] = { 0x81000000, 0x81000000, 0x81000000, 0x81000000, //Not used 0x81000000, 0x81000000, 0x81000000, 0x81000000, 0x81000000, 0x81000000, 0x01000000, 0x01000000, 0x81000000, 0x81000000, 0x81000000, 0x81000000 }; static long l_sfp3_feb_ctrl0[MAX_SLAVE] = { 0x01000000, 0x01000000, 0x01000000, 0x01000000, //Not used 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 }; //-------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------------- // bit 0 - 16 data sparsifying: bit 0: special channel, bit 1-16: adc channels // 0x00000: sparsifying disabled for all channles // 0x1fffe: sparsifying for all adc channels enabled // sparcifying for special channel disabled //-------------------------------------------------------------------------------------------------------- static long l_sfp0_feb_ctrl1[MAX_SLAVE] = { 0x00000, 0x1fffe, 0x1ff0e, 0x10ffe, //Not used 0x1effe, 0x1fffe, 0x1fffe, 0x1fffe, 0x1fffe, 0x1ff7e, 0x1fffe, 0x1fffe, 0x1effe, 0x1fffe, 0x1fffe, 0x1fffe }; static long l_sfp1_feb_ctrl1[MAX_SLAVE] = { 0x1fffe, 0x1fffe, 0x1fffe, 0x1fffe, 0x1fffe, //Only first five used 0x00000, 0x1fbfe, 0x1fefe, 0x1fefe, 0x1ff7e, 0x1ffbe, 0x1ffee, 0x00000, 0x00000, 0x00000, 0x00000 }; static long l_sfp2_feb_ctrl1[MAX_SLAVE] = { 0x00000, 0x00000, 0x00000, 0x00000, //Not used 0x00000, 0x00000, 0x00000, 0x00000, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff }; static long l_sfp3_feb_ctrl1[MAX_SLAVE] = { 0x0, 0x1ffff, 0x1ffff, 0x1ffff, //Not used 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff, 0x1ffff }; //-------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------------- // bit 0 - 15 internal trigger enable/disable for aadc channels 0-15 // 0x0000: trigger disabled for all adc channels // 0xffff: trigger enabled for all adc channels //-------------------------------------------------------------------------------------------------------- static long l_sfp0_feb_ctrl2[MAX_SLAVE] = { 0xffff, 0xffff, 0xffff, 0xffff, //Not used 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; static long l_sfp1_feb_ctrl2[MAX_SLAVE] = { 0xef00, 0x0000, 0x00ef, 0x00ef, //OR of pads 2, 4, and 6 + PD front and back 0xc02a, //Only first five used 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; static long l_sfp2_feb_ctrl2[MAX_SLAVE] = { 0xffff, 0xffff, 0xffff, 0xffff, //Not used 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; static long l_sfp3_feb_ctrl2[MAX_SLAVE] = { 0xffff, 0xffff, 0xffff, 0xffff, //Not used 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; //-------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------------- // max: 255 (adc counts) static long l_sfp0_thresh[MAX_SLAVE][FEBEX_CH] = { //Not used // channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 /* FEBEX 0 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 1 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 2 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 3 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 4 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 5 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 6 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 7 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 8 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 9 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 10 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 11 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 12 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 13 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 14 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 15 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff } }; // max: 255 (adc counts) static long l_sfp1_thresh[MAX_SLAVE][FEBEX_CH] = { // channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 / FEBEX 0 / { 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f }, / FEBEX 1 / { 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f }, / FEBEX 2 / { 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f }, / FEBEX 3 / { 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f }, / FEBEX 4 / { 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f, 0x85f }, / FEBEX 5 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 6 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 7 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 8 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 9 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 10 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 11 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 12 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 13 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 14 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, //Not used / FEBEX 15 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff } }; //Not used // max: 255 (adc counts) static long l_sfp2_thresh[MAX_SLAVE][FEBEX_CH] = { //Not used // channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 / FEBEX 0 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 1 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 2 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 3 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 4 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 5 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 6 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 7 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 8 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 9 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 10 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 11 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 12 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 13 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 14 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 15 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff } }; // max: 255 (adc counts) static long l_sfp3_thresh[MAX_SLAVE][FEBEX_CH] = { //Not used // channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 / FEBEX 0 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 1 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 2 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, / FEBEX 3 / { 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff }, ... 2280 more lines ...*
7	Tue Jun 28 17:42:53 2022	Guy Leckenby	DAQ	Cabling Changes
In the previous signal map, I incorrectly mapped the DSSD channels. To correctly read out the DSSD for the new test, we will swap the Lemo cables into the MSI-8, rather then messing with the flange. Hence, plug the old labels into the new channels as outlined in the attached table.
Attachment 1: DSSD_New_Ch.png

8	Fri Jul 29 15:33:08 2022	Guy Leckenby	Electronics	Results of Noise Testing
Uwe and I were able to get some noise testing done before the ESR was closed with asbestos exposure. We used the new flange so didn't address any issues with the old flange. Our main findings were: 1. majority of noise comes from the connection to the ESR. Compare the two scope pics attached with a) the detector isolated from the ESR, and b) the detector in the pocket. It is clear that the large high-frequency spikes of amplitude 40mV plus some low frequency modulation is coming from the ESR. 2. The signal loop for the MS Pads is through both the MPR-32s and the MSI-8s, so ensuring those preamps are collectively grounded is paramount. Having a short grounding cable that connects all of them to the NIM crate containing the preamp power supply is ideal. Wrapping in aluminium foil also seemed to help. a. Perhaps creating a Lemo to preamp ground signal would also help directly connect the flange to the preamps. 3. Shielding of the preamp cables seemed to help a bit, but not a huge amount. It may be worth investigating more the effects of shielding, but my feeling is that the above two sources are more important so shielding may not be worth the hassle. Remaining tasks to investigate: 1. Try and quantify impact of isolation from ESR by wrapping mounting system in Kapton tape. If this makes a big difference, perhaps we can create something more purpose built. 2. Quantify impact of noise on our signal from data analysis to see if its worth all this effort.
Attachment 1: PLEIADES_Noise_-_coupled_to_ESR.jpg

Attachment 2: PLEIADES_Noise_-_isolated_from_ESR.jpg

9	Mon Nov 7 14:14:38 2022	Chris Griffin, Guy Leckenby	Electronics	MSI-8 module details
MSI-8 module details. MMPR1 card configurations: - MMPR1_2000_50_V62hf_HV: 2GeV range, 20/60 MOhm bias resistors. 50us decay time. Batch # 37_20: 1/18 - 16/18. Dillmann PLEIADES CFI. - MMPR1_1G_25_V62_HV: 5GeV range, 20/60 MOhm bias resistors. 25us decay time. Batch # 42_13: 13/54 - 17/54, 21/54 - 28/54. Old LISA modules. - MMPR1_20G_25_V62_HV: 20GeV range, 2/11 MOhm bias resistors. 25us decay time. Batch # 29_13: 33/36 - 35/36. Old LISA modules. MSI-8 1+2: All 2GeV cards. MSI-8 3: Positions 1-5 are 5GeV cards, 6-8 are 20GeV cards MSI-8 4: All 5GeV cards
10	Fri Nov 11 10:27:59 2022	Chris Griffin, Guy Leckenby	Detectors	Current leakage currents
Attached are photos of leakage currents for the current GAGG and BGO setups. This setup uses the new flange (blue gas inlet), all pads are biased to +60V, the DSSD to +40V and the SiPD to +100V. Dry nitrogen from and LN2 dewar was flowing over the detectors. Attachment 1, GAGG housing. Contains: MSPad 17A - 310 nA DSSD 161054 - 249 nA MSPad 17B - 316 nA MSPad 17C - 334 nA MSPad 16A - 339 nA MSPad 16B - 361 nA MSPad 16C - 361 nA GAGG SiPD - 293 nA Attachment 2, BGO housing. Contains: Design-I 14 - 135 nA DSSD 121813 - 30 nA Design-I 13 - 583 nA MSPad 15B - 78 nA Empty - Design-I 6 - 586 nA Design-I 8 - 518 nA BGO SiPD - 162 nA
Attachment 1: Housing1-GAGG.jpg

Attachment 2: Housing2-BGO.jpg

11	Tue Nov 15 14:30:25 2022	Chris Griffin	Electronics	Old flange noise
Last week we tested both the new and old flanges with the GAGG housing set up described in the previous ELog entry. Performance of the new flange was excellent, with clear signal and low noise contribution. We didn't take any photos of this as it was so textbook. The old flange we identified as performing poorly in June was installed and we carried out the same pulser tests. This flange clearly creates a different noise environment and initially showed noise comparable/exceeding the 500mV pulser we were inputting. A photo of the scope signal from one of the pad detectors is shown in Attachment 1. We thought this could be due to the separate ground planes the MPR and MSI modules are on on the flange PCB so connected these ground planes together. This did not really improve the very noisy signal, but made the MSI-8 slightly worse. All-in-all, no significant improvement. We noted an electrical connection between the D-Sub connector housings and the L-brackets on the flange, connecting the D-Subs, their signal and grounds directly to the ring. Isolating them from the flange was as simple as applying some tape to the inside of the bracket. I installed the old flange in the ESR with the GAGG housing and the noise is dramatically improved. There remains some significant wobble in the signal baseline
Attachment 1: oldFlange-MPR.jpg

12	Thu Nov 17 13:42:16 2022	Chris Griffin	Detectors	Detector config changes
I have changed the configuration of Housing 2 (BGO) to account for the detector being fixed (bond wires) and provide a "plug-and-play" housing ready to go for any future experiments. The detector ordering is as follows: Slot 1 - Design-I #14 Slot 2 - Canberra DSSD 121813 Slot 3 - MSPad 15B Slot 4 - Design-I #13 Slot 5 - Design-I #8 Slot 6 - Design-I #6 Slot 7 - EMPTY Slot 8 - Design-I #3 Design-I #14 previously fell out of its frame during tests at TRIUMF. Its leakage current is comparable with other Design-I detectors but if real-world performance is different in future this may be the cause and the detector should be swapped out. The housing is also a little warped around the slots for the screws to attach the detector to the end of the flange arm due to overtightening of those screws. This makes inserting a detector into slot 5 very difficult for the first ~1cm and should be done with considerable care.
14	Mon May 29 12:23:48 2023	Guy Leckenby, Chris Griffin	Electronics	Old flange noise re-tests
Whilst constructing a new flange to replace the old one, we did some tests again to compare the performance of new vs old flange. See attached images: 1. Old flange, in the lab, no grounding attempts made, biased, n-sides. 2. Old flange, lab, ground plate connected to flange, biased n-sides. This comparison shows that for the old flange, connecting the ground plane to the flange improved the 50Hz noise. This was also true in the ESR, so all following screenshots had this ground connection. 3. Old flange, in the ESR, grounded, biased, n-sides. 4. Old flange, in the ESR, grounded, biased, p-sides. 5. New flange, in the ESR, biased, n-sides. Attachment 3 v 5 is an apples to apples comparison. This confirmed that even for the best case scenario, the noise in the old flange is an order of magnitude worse. Note that the n- sides have the worse profile, and for the old flange, the high frequency noise is almost the same size as the pulser. For the new flange, that same noise can be seen, but much smaller magnitude. Grounding on the new flange made no appreciable difference. But in general, we think connecting the electronic ground to the ESR is the best decision.
Attachment 1: 26.05.23-MHLab-Old_Flange_Biased_No_Grnd_Con_n-sides.PNG

Attachment 2: 26.05.23-MHLab-OF-B-YGC-n-sides.PNG

Attachment 3: 26.05.23-ESR-OF-B-YGC-n-sides.PNG

Attachment 4: 26.05.23-ESR-OF-B-YGC-p-sides.PNG

Attachment 5: 26.05.23-ESR-NF-B-NGC-n-sides.PNG

15	Thu Jun 1 09:39:24 2023	Guy Leckenby, Chris Griffin	Electronics	New new flange test
We tested the new new flange using the same setup as in ELOG entry 14. The noise level seemed to be somewhere between the middle flange and the old flange. See attachments: 1. Best noise conditions (grounding two planes and connection to ESR) on worst n-side pad. 2. Worse noise conditions (no grounding) on worst n-side. 3. Best noise conditions on a better n-side. We were unsure why some n-sides were different though. Thus, for a final comparison of the flanges (best conditions on n-sides): - 2016 flange - noise scale = ~5V - 2022 flange - noise scale = ~0.4V - 2023 flange - noise scale = ~0.8V
Attachment 1: 31.05.23-ESR-NNF-YGC-n-sides.PNG

Attachment 2: 31.05.23-ESR-NNF-NGC-n-sides.PNG

Attachment 3: 31.05.23-ESR-NNF-YGC-n-sides-v2.PNG

16	Thu Jun 1 10:42:31 2023	Guy Leckenby	Electronics	Summary of Preamp Testing
MSI-8 and MPR-16 preamps have nominal differential output ranges of +/-1.8V and +/-1.2V respectively at maximum input (ie 5GeV). All our FEBEX cards are now modified to accept +/-2V range. If serious pileup occurs, this could make it difficult to disentangle events for the n-sides. To test whether out preamps satisfied this output range, we attempted to calculate the expected height from a 500mV pulser. This should have been: input height * (pulser coupling range / preamp energy range) * nominal output range Mesytec noted that all coupling components are only tested to be within +/-10%, including the pulser coupling capacitors. Thus exact testing is challenging. The pulser inputs of our MSI-8 cards are: MMPR-1: Pulser inputs: Type: 2GeV Pulser : 330MeV/V Type: 5GeV Pulser : 330MeV/V Type: 20GeV Pulser: 1GeV/V Thus in the attached table, we can see the 2GeV and 5GeV cards are well within tolerance, but the 20GeV card is a bit outside. Thus we should probably expect a large output range from those cards. We also tested the MPR-16 cards. However these cards do not have a terminated pulser input, and it is not clear to us what impact that would have. In the attached table, it seems to have a pretty consistent factor of 4 difference though.
Attachment 1: preamp_tests.png

17	Tue Dec 12 12:57:16 2023	Jan	DAQ	test lmd-files with pulser
We took a few lmd-files with different settings of the febex DAQ to provide data for go4 development, when the DAQ is not running. The files are located at lxg1048:/data.local2/2023_pleiades timesorter_sparcifying.lmd - both nodes delivering data to the timesorter (sparcifying on) timesorter_traces.lmd - both nodes delivering data to the timesorter (sparcifying off) x86l-124_sparcifying.lmd - single node data (sparcifying on) x86l-124_traces.lmd - single node data (sparcifying off) x86l-131_sparcifying.lmd - single node data (sparcifying on) x86l-131_traces.lmd - single node data (sparcifying off) comment: Both systems run on a 70 Hz pulser via 4 MesyTec preamps into 3 febex cards. For unknown reasons x86l-124 delivers more data than x86l-131 when sparcifying is on. However, the threshold settings were not checked.

ELOG V3.1.5-fc6679b