/*  CAEN V785 32 channel ADC*/


#include "stdio.h"
#include "s_veshe.h"

//----------------------------------------------

#define MWPC_downscale 0    // reduction = 2**MWPC_downscale
#define SI_downscale 0  
#define VME_BASE 0x00000000

#define TB__OFFSET 0x05000000
#define TB__No_Ch 16
#define TB__No_Ch_enabled 16
#define TB__lmd_offset 0x300

#define ADC_V785__VME_OFFSET 0x00200000
#define ADC_V785__VME_SIZE 0x10000
#define ADC_V785__No_Ch 32
#define ADC_V785__lmd_offset 0x00
#define ADC_V785__No_Mod 3

#define SCA_V830_VME_OFFSET 0x00000000
#define SCA_V830_VME_SIZE 0x10000
#define SCA_V830__No_Ch 32
#define SCA_V830__lmd_offset 0x100

#define TDC_V1190a__OFFSET 0x01200000
#define TDC_V1190a__VME_SIZE 0x10000
#define TDC_V1190a__No_Ch  128
#define TDC_V1190a__No_hit_per_Ch 1 //only single hit allowed
#define TDC_V1190a__lmd_offset 0x200 
#define TDC_V1190a__win_width 200
#define TDC_V1190a__win_offset -180


const long TB_Ch_enable_reg_F_0 = 0x00FF ;

//------------//
// scale down: ch00, ch01, ch02
const long TB_scale_down_0_F[TB__No_Ch] ={ SI_downscale,MWPC_downscale,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0} ;

const long ADC_threshold_value = 0x0000 ;


/*****************************************************************************/

/*
 * all pointer wllhich are used for read/write operations in the functions
 * f_user_init and f_user_readout must be defined here as static variables
 */

static long volatile *pl_VME_virtual_mem_base ;
 
static long volatile *pl_trig_vme_str;   // triva status register


static  long ll_evt_ctr = 0;


/* TB - Triggerbox on Vulom3 */

static long volatile *pl_TB__base ;
static long volatile *pl_TB__Ch_enable_reg_F_0 ;
static long volatile *pl_TB__scale_down_7_0 ;
static long volatile *pl_TB__scale_down_F_8 ;
static long volatile *pl_TB__latch_reg ;
static long volatile *pl_TB__version ;
static long volatile *pl_TB__scaler_inp [TB__No_Ch];
static long volatile *pl_TB__scaler_inhib [TB__No_Ch] ;
static long volatile *pl_TB__scaler_after_reduction [TB__No_Ch] ;


long TB__scaler_inp_old [TB__No_Ch] = { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0} ;
long TB__scaler_inhib_old [TB__No_Ch] = { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0} ;
long TB__scaler_after_reduction_old [TB__No_Ch] = { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0} ;


/* ADC - Analog to Digital Converter CAEN V785AH */

static long volatile  *pl_ADC_V785__base [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__firm_rev [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__geo_adr [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__oui_msb [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__oui [ADC_V785__No_Mod]     ;
static short volatile *ps_ADC_V785__oui_lsb [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__version [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__board_id_msb [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__board_id  [ADC_V785__No_Mod]    ;
static short volatile *ps_ADC_V785__board_id_lsb [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__revision [ADC_V785__No_Mod] ;
static short volatile *ps_ADC_V785__serial_msb [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__serial_lsb [ADC_V785__No_Mod];

static long volatile *pl_ADC_V785__outp_buffer [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__bit_set_1 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__bit_clr_1 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__stat_reg_1 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__ctrl_reg_1 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__stat_reg_2 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__bit_set_2 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__bit_clr_2 [ADC_V785__No_Mod];
static short volatile *ps_ADC_V785__threshs[ADC_V785__No_Ch] [ADC_V785__No_Mod];





/* SCA - Scaler CAEN V830 */
static long volatile  *pl_SCA_V830__base;
static long volatile  *pl_SCA_V830__outp_buffer; 
static long volatile  *pl_SCA_V830__counter[SCA_V830__No_Ch];
static short volatile *ps_SCA_V830__scaler_clr;
static short volatile *ps_SCA_V830__scaler_status_reg;
static short volatile *ps_SCA_V830__fixed_code;
static short volatile *ps_SCA_V830__manuf_mod_type;
static short volatile *ps_SCA_V830__version_series;

static short volatile *ps_SCA_V830__firm_rev;
static short volatile *ps_SCA_V830__geo_adr;
static short volatile *ps_SCA_V830__oui_msb ;
static short volatile *ps_SCA_V830__oui     ;
static short volatile *ps_SCA_V830__oui_lsb ;
static short volatile *ps_SCA_V830__version ;
static short volatile *ps_SCA_V830__board_id_msb ;
static short volatile *ps_SCA_V830__board_id     ;
static short volatile *ps_SCA_V830__board_id_lsb ;
static short volatile *ps_SCA_V830__revision ;
static short volatile *ps_SCA_V830__serial_msb;
static short volatile *ps_SCA_V830__serial_lsb;
static short volatile *ps_SCA_V830__bit_set_1 ;
static short volatile *ps_SCA_V830__bit_clr_1 ;
static short volatile *ps_SCA_V830__stat_reg_1;
static short volatile *ps_SCA_V830__ctrl_reg_1;
static short volatile *ps_SCA_V830__sw_clr_reg ;

long SCA_V830__data_old [SCA_V830__No_Ch] ;





/* TDC - Time to Digital Converter CAEN V1190a  */

static long volatile  *pl_TDC_V1190a__base ;
static long volatile  *pl_TDC_V1190a__outp_buffer ;
static short volatile *ps_TDC_V1190a__ctrl_reg_1 ;
static short volatile *ps_TDC_V1190a__stat_reg_1 ;

static short volatile *ps_TDC_V1190a__geo_adr ;

static short volatile *ps_TDC_V1190a__module_reset ;
static short volatile *ps_TDC_V1190a__sw_clr ;
static short volatile *ps_TDC_V1190a__sw_evt_reset ;
static short volatile *ps_TDC_V1190a__sw_trig ;
static short volatile *pl_TDC_V1190a__evt_cnt ;

static short volatile *ps_TDC_V1190a__firmware_rev ;

static short volatile *ps_TDC_V1190a__micro_reg ;
static short volatile *ps_TDC_V1190a__micro_hdshk_reg ;


static short volatile *ps_TDC_V1190a__oui_2 ;
static short volatile *ps_TDC_V1190a__oui_1 ;
static short volatile *ps_TDC_V1190a__oui_0 ;

static short volatile *ps_TDC_V1190a__board_ver ;

static short volatile *ps_TDC_V1190a__board_id_2 ;
static short volatile *ps_TDC_V1190a__board_id_1 ;
static short volatile *ps_TDC_V1190a__board_id_0 ;

static short volatile *ps_TDC_V1190a__revision_3 ;
static short volatile *ps_TDC_V1190a__revision_2 ;
static short volatile *ps_TDC_V1190a__revision_1 ;
static short volatile *ps_TDC_V1190a__revision_0 ;

static short volatile *ps_TDC_V1190a__serial_1 ;
static short volatile *ps_TDC_V1190a__serial_0 ;







 
int l_mod;
int l_ch;

long  l_event_counter;



 
/*****************************************************************************/

/*****************************************************************************/

int f_user_get_virt_ptr (long  *pl_loc_hwacc, long  pl_rem_cam[])
{
 int  i;
 long l_i, l_j;
  
  /*
   * create virtual pointer to be used in f_user_init and f_user_readout
   */
 l_event_counter = 0;

  //***************
  // CAEN mapping
  //***************

 {  //#ifdef CAEN
  
  pl_VME_virtual_mem_base = (long*) ((long)pl_loc_hwacc) ;

 } //#endif // CAEN

// *****************************************************************************/


 {
   // * create virtual pointer to be used in f_user_init and f_user_readout
  
   
  
/*------------------------------------------------------------------------------*/
/*                                TB on VULOM3                                  */
/*------------------------------------------------------------------------------*/
 
 
  {
   pl_TB__base  = (long*) ((long) pl_VME_virtual_mem_base + TB__OFFSET ) ;  

   pl_TB__Ch_enable_reg_F_0   = (long*) ( (long) pl_TB__base + 0x0000 );
   pl_TB__scale_down_7_0      = (long*) ( (long) pl_TB__base + 0x0004 ); 
   pl_TB__scale_down_F_8      = (long*) ( (long) pl_TB__base + 0x0008 ) ; 
   pl_TB__latch_reg           = (long*) ( (long) pl_TB__base + 0x000c ); 
   pl_TB__version             = (long*) ( (long) pl_TB__base + 0x003c );
   long l_ch ;
   
   for (l_ch=0; l_ch<TB__No_Ch; l_ch++)
    { pl_TB__scaler_inp[l_ch] =  
        (long*) ( (long) pl_TB__base + 0x0040 +(l_ch*4)); 
      pl_TB__scaler_inhib[l_ch] =  
        (long*) ( (long) pl_TB__base + 0x0080 +(l_ch*4)); 
      pl_TB__scaler_after_reduction[l_ch] =  
        (long*) ( (long) pl_TB__base + 0x00c0 +(l_ch*4)); 
    }
  }

   
   
   
   
   
   
/*------------------------------------------------------------------------------*/
/*                                ADC CAEN 785AH                                */
/*------------------------------------------------------------------------------*/

  for (l_mod = 0 ; l_mod < ADC_V785__No_Mod; l_mod++)
  {
   pl_ADC_V785__base[l_mod]  = (long*) ( (long) pl_VME_virtual_mem_base + ADC_V785__VME_OFFSET + l_mod * ADC_V785__VME_SIZE) ;

   
   ps_ADC_V785__firm_rev[l_mod]  = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1000 );
   ps_ADC_V785__geo_adr[l_mod]   = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1002 );
   ps_ADC_V785__oui_msb[l_mod]   = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x8026 );
   ps_ADC_V785__oui[l_mod]       = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x802a );
   ps_ADC_V785__oui_lsb[l_mod]   = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x802e );
   ps_ADC_V785__version[l_mod]   = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x8032 );
   ps_ADC_V785__board_id_msb[l_mod]= (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x8036 );
   ps_ADC_V785__board_id[l_mod]    = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x802a );
   ps_ADC_V785__board_id_lsb[l_mod]= (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x802e );
   ps_ADC_V785__revision[l_mod]   =   (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x804e );
   ps_ADC_V785__serial_msb[l_mod] = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x8f02 );
   ps_ADC_V785__serial_lsb[l_mod] = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x8f06 );

   pl_ADC_V785__outp_buffer[l_mod]=  (long*) ( (long) pl_ADC_V785__base[l_mod] + 0x0000 );
   ps_ADC_V785__bit_set_1[l_mod]  =   (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1006 );
   ps_ADC_V785__bit_clr_1[l_mod]  =   (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1008 );
   ps_ADC_V785__stat_reg_1[l_mod] =  (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x100e );
   ps_ADC_V785__ctrl_reg_1[l_mod] =  (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1010 );
   ps_ADC_V785__stat_reg_2[l_mod] =  (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1022 );
   ps_ADC_V785__bit_set_2[l_mod]  =   (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1032 );
   ps_ADC_V785__bit_clr_2[l_mod]  =   (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1034 );

   for (l_ch=0; l_ch<ADC_V785__No_Ch; l_ch++)
   {
    ps_ADC_V785__threshs[l_ch][l_mod] = (short*) ( (long) pl_ADC_V785__base[l_mod] + 0x1080 + l_ch * 0x0002 );
   }
  } 
  
/*------------------------------------------------------------------------------*/
/*                                Scaler CAEN V830                                */
/*------------------------------------------------------------------------------*/
  
  {
   pl_SCA_V830__base            = (long*) ( (long) pl_VME_virtual_mem_base + SCA_V830_VME_OFFSET ) ;
   pl_SCA_V830__outp_buffer     = (long*)  ( (long) pl_SCA_V830__base + 0x0000 ); 
   ps_SCA_V830__firm_rev        = (short*) ( (long) pl_SCA_V830__base + 0x1132 );
   ps_SCA_V830__geo_adr         = (short*) ( (long) pl_SCA_V830__base + 0x1110 );
   ps_SCA_V830__oui_msb         = (short*) ( (long) pl_SCA_V830__base + 0x4026 );
   ps_SCA_V830__oui             = (short*) ( (long) pl_SCA_V830__base + 0x402a );
   ps_SCA_V830__oui_lsb         = (short*) ( (long) pl_SCA_V830__base + 0x402e );
   ps_SCA_V830__version         = (short*) ( (long) pl_SCA_V830__base + 0x4032 );
   ps_SCA_V830__board_id_msb    = (short*) ( (long) pl_SCA_V830__base + 0x4036 );
   ps_SCA_V830__board_id        = (short*) ( (long) pl_SCA_V830__base + 0x402a );
   ps_SCA_V830__board_id_lsb    = (short*) ( (long) pl_SCA_V830__base + 0x402e );
   ps_SCA_V830__revision        = (short*) ( (long) pl_SCA_V830__base + 0x404e );
   ps_SCA_V830__serial_msb      = (short*) ( (long) pl_SCA_V830__base + 0x4f02 );
   ps_SCA_V830__serial_lsb      = (short*) ( (long) pl_SCA_V830__base + 0x4f06 );
  
   long l_ch ;
  
   for (l_ch=0; l_ch<SCA_V830__No_Ch; l_ch++)
   { 
    pl_SCA_V830__counter[l_ch] = (long*) ( (long) pl_SCA_V830__base + 0x1000 +(l_ch*4)); 
   }
   ps_SCA_V830__bit_set_1       = (short*) ( (long) pl_SCA_V830__base + 0x110a );
   ps_SCA_V830__bit_clr_1       = (short*) ( (long) pl_SCA_V830__base + 0x110c );
   ps_SCA_V830__stat_reg_1      = (short*) ( (long) pl_SCA_V830__base + 0x110e );
   ps_SCA_V830__ctrl_reg_1      = (short*) ( (long) pl_SCA_V830__base + 0x1108 );
   ps_SCA_V830__sw_clr_reg      = (short*) ( (long) pl_SCA_V830__base + 0x1122 );
  }
    
  /*------------------------------------------------------------------------------*/
/*                                TDC_V1190a CAEN V1190a                        */
/*------------------------------------------------------------------------------*/

 
 {
  pl_TDC_V1190a__base  = (long*) ( (long) pl_VME_virtual_mem_base + TDC_V1190a__OFFSET ) ;  
  pl_TDC_V1190a__outp_buffer     = (long*)  ( (long) pl_TDC_V1190a__base +0x0000) ;  
  ps_TDC_V1190a__ctrl_reg_1      = (short*) ( (long) pl_TDC_V1190a__base +0x1000) ;  
  ps_TDC_V1190a__stat_reg_1      = (short*) ( (long) pl_TDC_V1190a__base +0x1002) ;    
  ps_TDC_V1190a__geo_adr         = (short*) ( (long) pl_TDC_V1190a__base +0x100e) ; 
  ps_TDC_V1190a__module_reset    = (short*) ( (long) pl_TDC_V1190a__base +0x1014) ;  
  ps_TDC_V1190a__sw_clr          = (short*) ( (long) pl_TDC_V1190a__base +0x1016) ;  
  ps_TDC_V1190a__sw_evt_reset    = (short*) ( (long) pl_TDC_V1190a__base +0x1018) ;  
  ps_TDC_V1190a__sw_trig         = (short*) ( (long) pl_TDC_V1190a__base +0x101a) ;
  pl_TDC_V1190a__evt_cnt         = (short*) ( (long) pl_TDC_V1190a__base +0x101c) ;
  ps_TDC_V1190a__firmware_rev    = (short*) ( (long) pl_TDC_V1190a__base +0x1026) ;
  ps_TDC_V1190a__micro_reg       = (short*) ( (long) pl_TDC_V1190a__base +0x102e) ;
  ps_TDC_V1190a__micro_hdshk_reg = (short*) ( (long) pl_TDC_V1190a__base +0x1030) ;
    
  ps_TDC_V1190a__oui_2           = (short*) ( (long) pl_TDC_V1190a__base +0x4024) ;
  ps_TDC_V1190a__oui_1           = (short*) ( (long) pl_TDC_V1190a__base +0x4028) ;
  ps_TDC_V1190a__oui_0           = (short*) ( (long) pl_TDC_V1190a__base +0x402c) ;

  ps_TDC_V1190a__board_ver       = (short*) ( (long) pl_TDC_V1190a__base +0x4030) ;  
  
  ps_TDC_V1190a__board_id_2      = (short*) ( (long) pl_TDC_V1190a__base +0x4034) ;
  ps_TDC_V1190a__board_id_1      = (short*) ( (long) pl_TDC_V1190a__base +0x4038) ;
  ps_TDC_V1190a__board_id_0      = (short*) ( (long) pl_TDC_V1190a__base +0x403c) ;
 
  ps_TDC_V1190a__revision_3      = (short*) ( (long) pl_TDC_V1190a__base +0x4040) ;
  ps_TDC_V1190a__revision_2      = (short*) ( (long) pl_TDC_V1190a__base +0x4044) ;
  ps_TDC_V1190a__revision_1      = (short*) ( (long) pl_TDC_V1190a__base +0x4048) ;
  ps_TDC_V1190a__revision_0      = (short*) ( (long) pl_TDC_V1190a__base +0x404c) ;


 ps_TDC_V1190a__serial_0         = (short*) ( (long) pl_TDC_V1190a__base +0x4080) ;
 ps_TDC_V1190a__serial_1         = (short*) ( (long) pl_TDC_V1190a__base +0x4084) ;

 }
 // END of TDC_V1190a   
    
     
    
    
 }

}             /* End of f_user_get_virt_ptr */
/*****************************************************************************/
/****************************************************************************/



#define TIMEOUT 1000000




 /*-------------------------------------------------------------*/

 
 
 
/*
 * write opcode to TDC
 */

int write_op_V1190a( unsigned short data)
{
  unsigned short rdata;
  

  printf ("write_op handshake wait for write okay \n");
  fflush(stdout);

  do
  {
    usleep(500000);
    rdata = *ps_TDC_V1190a__micro_hdshk_reg;
    printf ("write_op handshake:  0x%x \n", rdata);
    fflush(stdout);
  }
   while ((rdata != 0x01) );
    
      printf ("write_op data:       0x%x \n", data);
      fflush(stdout);
  
    *ps_TDC_V1190a__micro_reg = data;
	usleep(500000);
	
  printf ("write okay... \n");
  fflush(stdout);	
	
  return 0;
}



int read_op_V1190a ( unsigned short data)
{
 unsigned short rdata ;
 
 do
  {
    rdata = *ps_TDC_V1190a__micro_hdshk_reg;
  }
 while ( (rdata != 0x02) ) ;
  data = *ps_TDC_V1190a__micro_reg ;
  sleep(1); 
 return(0);
} 

 


 /*-------------------------------------------------------------*/



int f_user_init (unsigned char  bh_crate_nr,
                 long           *pl_loc_hwacc,
                 long           *pl_rem_cam,
                 long           *pl_stat)

{

 
 int l_ch;
 long l_dummy;
// unsigned short rdata;
// unsigned short opcbuffer;
 
 short win_offs, win_width;
  int threshold_value;

 switch (bh_crate_nr)
 {
  case 0:
  {
    
  
/* SET TB on VULOM3 initial parameters */


   printf (" \n \n \n");
   printf ("-----------------------------------------\n");
   printf ("Setup TB on VULOM3      \n");
   printf ("                      \n");
  
   printf ("set Channel enable register F..0:   0x%x  \n", TB_Ch_enable_reg_F_0);
   fflush(stdout);
   *pl_TB__Ch_enable_reg_F_0 = TB_Ch_enable_reg_F_0 ;
   printf ("done. \n\n");
   fflush(stdout);

   printf ("set Channel Scale down register  \n");
   fflush(stdout);
   
   *pl_TB__scale_down_7_0 = 
    ((TB_scale_down_0_F[7]&0x000f) << 28) +
    ((TB_scale_down_0_F[6]&0x000f) << 24) +
    ((TB_scale_down_0_F[5]&0x000f) << 20) +
    ((TB_scale_down_0_F[4]&0x000f) << 16) +
    ((TB_scale_down_0_F[3]&0x000f) << 12) +
    ((TB_scale_down_0_F[2]&0x000f) << 8 )+
    ((TB_scale_down_0_F[1]&0x000f) << 4 )+
    ((TB_scale_down_0_F[0]&0x000f)) ;
 
   *pl_TB__scale_down_F_8 = 0;    
    (TB_scale_down_0_F[15]&0x000f) << 28 +
    (TB_scale_down_0_F[14]&0x000f) << 24 +
    (TB_scale_down_0_F[13]&0x000f) << 20 +
    (TB_scale_down_0_F[12]&0x000f) << 16 +
    (TB_scale_down_0_F[11]&0x000f) << 12 +
    (TB_scale_down_0_F[10]&0x000f) << 8 +
    (TB_scale_down_0_F[9]&0x000f) << 4 +
    (TB_scale_down_0_F[8]&0x000f) ;

    
     
   printf ("done. \n\n");
   fflush(stdout);
   
    
    
   
    
   for (l_mod=0; l_mod< ADC_V785__No_Mod; l_mod++) 
   {
    printf (" \n\n\n");
    printf ("ADC_V785 No: %d                   Try to access modul identifier words. \n",l_mod);
    printf ("ADC_V785 Firmware Revision:  0x%x \n", (*ps_ADC_V785__firm_rev[l_mod]& 0xffff));
    printf ("ADC_V785 Geo Adress:         0x%x , dezimal: %d \n", (*ps_ADC_V785__geo_adr[l_mod] & 0x001f), (*ps_ADC_V785__geo_adr[l_mod] & 0x001f));
    printf ("ADC_V785 Manufacturer ID:    0x%x 0x%x 0x%x \n", (*ps_ADC_V785__oui_msb[l_mod]& 0xff), (*ps_ADC_V785__oui[l_mod]& 0xff), (*ps_ADC_V785__oui_lsb[l_mod]& 0xff));
    printf ("ADC_V785 Version:            0x%x \n", (*ps_ADC_V785__version[l_mod]& 0xff));
    printf ("ADC_V785 Board ID:           0x%x 0x%x 0x%x \n", (*ps_ADC_V785__board_id_msb[l_mod]& 0xff), (*ps_ADC_V785__board_id[l_mod]& 0xff), (*ps_ADC_V785__board_id_lsb[l_mod]& 0xff));
    printf ("ADC_V785 Hardware Revision:  0x%x \n", (*ps_ADC_V785__revision[l_mod]& 0xff));
    printf ("ADC_V785 Module Serial No:   0x%x 0x%x \n", (*ps_ADC_V785__serial_msb[l_mod]& 0xff), (*ps_ADC_V785__serial_msb[l_mod]& 0xff));

    printf ("ADC_V785 No.:                Memory access test finished. \n");
    printf ("                            \n");
   } 

   
   {
    printf (" \n\n\n");
    printf ("SCA_V830                     Try to access modul identifier words. \n");
    printf ("SCA_V830 Firmware Revision:  0x%x \n", (*ps_SCA_V830__firm_rev& 0xffff));
    printf ("SCA_V830 Geo Adress:         0x%x , dezimal: %d \n", (*ps_SCA_V830__geo_adr & 0x001f), (*ps_SCA_V830__geo_adr & 0x001f));
    printf ("SCA_V830 Manufacturer ID:    0x%x 0x%x 0x%x \n", (*ps_SCA_V830__oui_msb& 0xff), (*ps_SCA_V830__oui& 0xff), (*ps_SCA_V830__oui_lsb& 0xff));
    printf ("SCA_V830 Version:            0x%x \n", (*ps_SCA_V830__version& 0xff));
    printf ("SCA_V830 Board ID:           0x%x 0x%x 0x%x \n", (*ps_SCA_V830__board_id_msb& 0xff), (*ps_SCA_V830__board_id& 0xff), (*ps_SCA_V830__board_id_lsb& 0xff));
    printf ("SCA_V830 Hardware Revision:  0x%x \n", (*ps_SCA_V830__revision& 0xff));
    printf ("SCA_V830 Module Serial No:   0x%x 0x%x \n", (*ps_SCA_V830__serial_msb& 0xff), (*ps_SCA_V830__serial_msb& 0xff));
    printf ("SCA_V830 No.:                Memory access test finished. \n");
    printf ("                            \n");
   }    
   
   
   

/*--------------------------------------------------------------------------*/
/*                                                                          */
/*                   INIT HARDWARE                                          */
/*                                                                          */
/*--------------------------------------------------------------------------*/



// ADC CAEN V785AH set initial parameters
   for (l_mod=0; l_mod< ADC_V785__No_Mod; l_mod++) 
   {
    printf (" \n \n \n");
    printf ("-----------------------------------------\n");
    printf ("ADC V785AH No: %d                \n",l_mod);
    printf ("                           \n");
    printf ("ADC SETUP \n ") ;
/* SET PROG EMPTY FLAG for ADC_V785  */
    *ps_ADC_V785__bit_set_2[l_mod]  = 0x1000; // even if no data was measured there will be header and trailer written to buffer
    //     *ps_ADC_V785__bit_clr_2 [l_mod] = 0x1000; // if no data are measured there will be NO header or trailer written to buffer
    printf ("Set ADC785AH to enable Header and Trailer in data structure \n");
    fflush(stdout);

//  switch on the over range flag, data will be written in any case 
    *ps_ADC_V785__bit_set_2[l_mod] = 0x0008 ;
 


/* SET ADC_V785-THRESHOLDs */
    threshold_value= ADC_threshold_value;
    for (l_ch=0; l_ch <  ADC_V785__No_Ch; l_ch++)
    {
     *ps_ADC_V785__threshs[l_ch][l_mod] = threshold_value;  // set lower threshold for accepted ADC values
    } 
    printf ("Set ADC785AH lower threshold to 0x%x \n", threshold_value);
    fflush(stdout);
         
 /* ADC_V785 DATA CLEAR */
    *ps_ADC_V785__bit_set_2[l_mod]=0x04;
    *ps_ADC_V785__bit_clr_2[l_mod]=0x04;
    printf ("Perform ADC V785AH buffer clear \n");
    fflush(stdout);
   }
// End of ADC Setup	  




   { // Scaler SCA_V830:  V830 set initial parameters    
    printf (" \n \n \n");
    printf ("-----------------------------------------\n");
    printf ("SCA V830:                \n");
    printf ("                           \n");
    printf ("SCA SETUP \n") ;
//      set V830 to default settings
    *ps_SCA_V830__bit_clr_1 = 0x00FF;      
// set to random trigger mode, this is latch scalers when trigger on input
    *ps_SCA_V830__bit_set_1 = 0x0001;
    printf ("Set SCA V830 to external trigger mode \n");
    fflush(stdout);
// set to auto reset of counters after trigger DO NOT USE !!!
//      *ps_SCA_V830__bit_set_1 = 0x0080;
//       printf ("Set SCA V830 to auto reset of counters after trigger \n");
//       fflush(stdout);

// set enable scaler header written to listmode 
    *ps_SCA_V830__bit_set_1 = 0x0020;
    printf ("Set SCA V830 to enable scaler header output \n");
    fflush(stdout);
// set to 32-bit scaler dataformat
    *ps_SCA_V830__bit_clr_1 = 0x0004;
    printf ("Set SCA V830 to 32 bit counter format \n");
    fflush(stdout);
// software clear of all scalers 
    *ps_SCA_V830__sw_clr_reg = 1; 
    printf ("Perform SCA V830 counter clear \n");
    fflush(stdout);
   }  // End of Scaler Setup
 
// Last Scaler Clear before measurement		
   *ps_SCA_V830__sw_clr_reg = 1; 
   printf ("\nPerform SCA V830 Counter Register clear \n\n");
   fflush(stdout);

   for (l_ch=0; l_ch< SCA_V830__No_Ch; l_ch++)
   {
    SCA_V830__data_old [l_ch]=0;   
   } 
 
   

      {
         printf (" \n");

         printf ("TDC_V1190a                     Try to access modul identifier words. \n");
         printf ("TDC_V1190a Memory Adress:      0x%x \n", (pl_TDC_V1190a__base));

         printf ("TDC_V1190a Geo Adress:         0x%x , dezimal: %d \n", (*ps_TDC_V1190a__geo_adr & 0x001f), (*ps_TDC_V1190a__geo_adr & 0x001f));
         printf ("TDC_V1190a Manufacturer ID:    0x%x 0x%x 0x%x \n", (*ps_TDC_V1190a__oui_2& 0xff), (*ps_TDC_V1190a__oui_1& 0xff), (*ps_TDC_V1190a__oui_0& 0xff));
         printf ("TDC_V1190a Board Version (0x00:A , 0x01:B):   0x%x \n", (*ps_TDC_V1190a__board_ver& 0xff));
         printf ("TDC_V1190a Board ID:           0x%x 0x%x 0x%x \n", (*ps_TDC_V1190a__board_id_2& 0xff), (*ps_TDC_V1190a__board_id_1& 0xff), (*ps_TDC_V1190a__board_id_0& 0xff));
         printf ("TDC_V1190a Board Revision      0x%x 0x%x 0x%x 0x%x \n", (*ps_TDC_V1190a__revision_3& 0xff),( *ps_TDC_V1190a__revision_2& 0xff),( *ps_TDC_V1190a__revision_1& 0xff),( *ps_TDC_V1190a__revision_0& 0xff));
         printf ("TDC_V1190a Module Serial No:   0x%x 0x%x \n", (*ps_TDC_V1190a__serial_1& 0xff), (*ps_TDC_V1190a__serial_0& 0xff));
         printf ("TDC_V1190a Firmware Version:   0x%x \n", (*ps_TDC_V1190a__firmware_rev & 0xff));

         printf ("TDC_V1190a No.:                Memory access test finished. \n");
         printf ("                            \n");
       } 

 


/*--------------------------------------------------------------------------*/
/*                                                                          */
/*                   INIT HARDWARE                                          */
/*                                                                          */
/*--------------------------------------------------------------------------*/


/* SET TDC CAEN V1190a set initial parameters */


       {
         printf (" \n \n \n");
         printf ("-----------------------------------------\n");
         printf ("TDC V1190a:                \n");
         printf ("                           \n");
         printf ("TDC SETUP \n\n") ;
 
	 printf ("Software clr: Perform module reset. \n");
	 fflush(stdout);
         *ps_TDC_V1190a__module_reset=0x0;
    	 sleep(1);
	 printf ("Software clr done. \n\n");
         fflush(stdout);

         printf ("\nset TDC to Trigger Match Mode \n") ;
         write_op_V1190a(0x0000);
	 
         printf ("\nset disable TDC header and trailer \n") ;
         write_op_V1190a(0x3100);
	 
//         printf ("set enable subtraction of TDC trigger time \n") ;
//         write_op(0x1400);
         printf ("\nset disable subtraction of TDC trigger time \n") ;
         write_op_V1190a(0x1500);
	 
	 
         printf ("\nset TDC Trigger Window Width \n") ;
	 fflush(stdout);
         win_width = TDC_V1190a__win_width;  /* number * 25nsec */
         write_op_V1190a(0x1000);
	 write_op_V1190a(win_width);
		 
      printf (" Trigger Window Width set to 25ns x %d \n ",win_width);
      fflush(stdout);
	 
	 
       // TDC can look up to 52 micro sec (win_offs=-2000) into the past and 1 micro second (win_offs=+40) into the future
       // 
	 printf (" \n");
         printf ("set TDC Trigger Offset \n") ;
	 fflush(stdout);
         win_offs = TDC_V1190a__win_offset;  /* number * 25nsec */
         write_op_V1190a(0x1100);
         write_op_V1190a(win_offs);
         printf ("Trigger Window Offset set to 25ns x %d \n",win_offs);
	 
         fflush(stdout);
	 
         printf (" \n");
	 
	 usleep(30);
         printf ("Perform TDC V1190a Software clr: Perform module reset. \n");
         *ps_TDC_V1190a__sw_clr = 0; 
        

   }
// End of TDC Setup	  
   
   
  }    
  break;
  default:
 break;
 }
return (1);
}

/*****************************************************************************/



int f_user_readout (unsigned char  bh_trig_typ,
                    unsigned char  bh_crate_nr,
                    register long  *pl_loc_hwacc,
                    register long  *pl_rem_cam,
                    long           *pl_dat,
                    s_veshe        *ps_veshe,
                    long           *l_se_read_len,
                    long           *l_read_stat)
{
 // var definition

 long  l_chan_nr;
 long  l_event;
 long  l_No_of_events;
 long  l_No_of_events_mod;
 long  l_mod;
 long  l_ch;
 long  l_kill_event;
 long  l_dummy;
  
 long  l_ADC_V785__ch;
 long  l_ADC_V785__val;
// long  l_ADC_V785__header;
 long  l_ADC_V785__buffer_h;
 long  l_ADC_V785__buffer;
// long  l_ADC_V785__eo_block;
 long SCA_V830__data_tmp  ;  
 
 long  l_hits[TDC_V1190a__No_Ch];
 long  l_TDC_V1190a__ch_high;
 long  l_TDC_V1190a__ch_low;
 long  l_TDC_V1190a__val_high;
 long  l_TDC_V1190a__val_low;
 
 long  l_TDC_V1190a__header;
 long  l_TDC_V1190a__buffer[TDC_V1190a__No_Ch  * 2 ];
 long  l_TDC_V1190a__buffer_h;
 long  l_TDC_V1190a__eo_block;
 
 
 
 
 
 *l_se_read_len = 0;
 l_kill_event = 0; 
 l_event_counter++ ;
 ll_evt_ctr++;

 switch (bh_crate_nr)
 {
  case 0:
  switch (bh_trig_typ)
  {
    case 1 :
    case 2 :
    case 3 :
    case 4 :
     {
// TB_readout

   long l_TB_buffer_h;
   long l_TB_scaler_inp;
   long l_TB_scaler_inhibit; 
   long l_TB_scaler_after_reduction;
      
       
         *pl_TB__latch_reg = 1 ; //transfer of data to read register

         for (l_ch=0; l_ch<TB__No_Ch_enabled; l_ch++)
          {
           l_TB_buffer_h = *pl_TB__scaler_inp[l_ch];
  
	   l_TB_scaler_inp = l_TB_buffer_h ;
           l_TB_buffer_h = l_TB_buffer_h - TB__scaler_inp_old [l_ch];
           TB__scaler_inp_old [l_ch] = l_TB_scaler_inp ;
	   
           *pl_dat++ =  (( l_TB_buffer_h & 0xFFFF0000) +  TB__lmd_offset )+(2 * l_ch) ;  
           *l_se_read_len += 4;   
           *pl_dat++ =  ((( l_TB_buffer_h & 0x0000FFFF) << 16) +  TB__lmd_offset)+(2 * l_ch)+1 ;  
           *l_se_read_len += 4;   
          } 
         for (l_ch=0; l_ch<TB__No_Ch_enabled; l_ch++)
          {
           l_TB_buffer_h = *pl_TB__scaler_inhib[l_ch];

	   l_TB_scaler_inhibit = l_TB_buffer_h ;
           l_TB_buffer_h = l_TB_buffer_h - TB__scaler_inhib_old [l_ch];
           TB__scaler_inhib_old [l_ch] = l_TB_scaler_inhibit ;
 	   
           *pl_dat++ =  (( l_TB_buffer_h & 0xFFFF0000) +  TB__lmd_offset+ 0x00000080 )+(2 * l_ch) ;  
           *l_se_read_len += 4;   
           *pl_dat++ =  ((( l_TB_buffer_h & 0x0000FFFF) << 16) +  TB__lmd_offset+ 0x00000080)+(2 * l_ch)+1 ;  
           *l_se_read_len += 4;   
          } 
         for (l_ch=0; l_ch<TB__No_Ch_enabled; l_ch++)
          {
           l_TB_buffer_h = *pl_TB__scaler_after_reduction[l_ch];
	   
	   l_TB_scaler_after_reduction = l_TB_buffer_h ;
           l_TB_buffer_h = l_TB_buffer_h - TB__scaler_after_reduction_old [l_ch];
           TB__scaler_after_reduction_old [l_ch] = l_TB_scaler_after_reduction ;
   	   
           *pl_dat++ =  (( l_TB_buffer_h & 0xFFFF0000) +  TB__lmd_offset+ 0x00000100 )+(2 * l_ch) ;  
           *l_se_read_len += 4;   
           *pl_dat++ =  ((( l_TB_buffer_h & 0x0000FFFF) << 16) +  TB__lmd_offset+ 0x00000100)+(2 * l_ch)+1 ;  
           *l_se_read_len += 4;   
          } 
// TB_readout end 
     
// READOUT ADC V785AH
   
    for (l_mod=0; l_mod<ADC_V785__No_Mod; l_mod++)
    {
     l_dummy= 0;
		   
/* check for data*/
     if  (*ps_ADC_V785__stat_reg_1[l_mod] & 0x0001==1)  
     {
/* read first header */
      l_ADC_V785__buffer_h= *pl_ADC_V785__outp_buffer[l_mod];
        
/* number of ADC DATA: */
//              l_No_of_events=(l_ADC_V785__buffer_h & 0x00003fff) >>8;

/* readout data and put it into event buffer */        
      do 
      {
//read data word fromm adc buffer
       l_ADC_V785__buffer_h= *pl_ADC_V785__outp_buffer[l_mod];			  
			  
// if HEADER then do nothing
       if (((l_ADC_V785__buffer_h >> 24) & 0x07 ) == 0x02 ) 
       {
       }

// read ADC data   
       if (((l_ADC_V785__buffer_h >> 24) & 0x07 ) == 0x00 ) 
       {
	l_ADC_V785__ch = ((l_ADC_V785__buffer_h & 0x001f0000) >> 16) ;

//  isolate underflow bit,  overflow bit and adc data
        l_ADC_V785__val = (l_ADC_V785__buffer_h & 0x00003fff);
	*pl_dat++ = ((l_ADC_V785__val<<16)+  l_ADC_V785__ch + l_mod*ADC_V785__No_Ch + ADC_V785__lmd_offset);
	*l_se_read_len += 4;
       }

// if TRAILER then do nothing
       if (((l_ADC_V785__buffer_h >> 24) & 0x07 ) == 0x04 ) 
       {
       }
      }
      while (((l_ADC_V785__buffer_h >> 24 )& 0x07 ) != 0x04) ;
			  
// test if buffer is empty to avoid pile up 			            
      if  (*ps_ADC_V785__stat_reg_1[l_mod] & 0x0001==1)  
      { 
       printf ("\n\nPileup: ADC_V785 Buffer not empty after readout. Reseting Buffer. \n ");
       /* ADC_V785 DATA CLEAR */
       *ps_ADC_V785__bit_set_2[l_mod] = 0x04;
       *ps_ADC_V785__bit_clr_2[l_mod] = 0x04;
       printf ("\n\n");
      }
     }
    }
    
    
    
    {

    
//    READOUT V830       
//    ------------------------------------------------------
//
//    readout with trigger: CAEN calls it random triggering
//
//    ------------------------------------------------------
     long  l_dummy;
     long  l_value;
     long l_SCA_V830__buffer_h;
     l_SCA_V830__buffer_h = 0 ;
     l_dummy = 0 ; //test variable if data was in the event

// start of readout loop over all hits and additional data of this event read from the buffer MEB
     if ((*ps_SCA_V830__stat_reg_1 & 0x0001)==1)
     { 
      l_SCA_V830__buffer_h = *pl_SCA_V830__outp_buffer;
//   GLOBAL HEADER
      
//      printf ("\n header: %x \n ",(long)(l_SCA_V830__buffer_h ));
//      fflush(stdout);    
 
      if (((l_SCA_V830__buffer_h >> 26) & 0x0001 ) == 0x0001 ) 
      { ;				  
//   if header then do readout loop  		 	  
      
//      printf ("\n eventno: %d \n ",(long)(l_SCA_V830__buffer_h & 0x0000FFFF));
//      fflush(stdout);      
      
       long  l_ch;
       for (l_ch=0; l_ch<32; l_ch++)
       {
//   SCA DATA: write data to listmode file 

        l_SCA_V830__buffer_h = *pl_SCA_V830__outp_buffer;
	
//        printf ("eventdata: %d \n ",(long)(l_SCA_V830__buffer_h ));
//        fflush(stdout);      
	
	l_value = l_SCA_V830__buffer_h;
	SCA_V830__data_tmp = l_value;
	l_value = l_value - SCA_V830__data_old [l_ch];
	SCA_V830__data_old [l_ch] = SCA_V830__data_tmp ;
	
	
        *pl_dat++ =  (( l_value & 0xFFFF0000) +  SCA_V830__lmd_offset )+(2 * l_ch) ;  
        *l_se_read_len += 4;   
        *pl_dat++ =  ((( l_value & 0x0000FFFF) << 16) +  SCA_V830__lmd_offset )+(2 * l_ch)+1 ;  
        *l_se_read_len += 4;   
        l_dummy++;
       }
      }
     }
// check if SCA buffer is empty after readout          
     if ((*ps_SCA_V830__stat_reg_1 & 0x00000001)==1)
     { 
      printf ("PILEUP: SCA_V830 buffer not empty! Serious problem! Maybe, instable trigger!!!!!!!!!!!!!\n"); 
      fflush(stdout);          
      *ps_SCA_V830__sw_clr_reg = 0; 
      printf ("PILEUP: SCA_V830 buffer cleared!\n\n"); 
      fflush(stdout);          
     }  
    } // END of SCA V830 readout
    
    
    
 {

 

// READOUT TDC V1190a
   
// printf (" Event start \n ");
// fflush(stdout);
        
    l_TDC_V1190a__header = 0 ;
    l_TDC_V1190a__eo_block = 0;
    for (l_ch=0; l_ch<TDC_V1190a__No_Ch; l_ch++)
     {
      l_TDC_V1190a__ch_high = l_ch * 2 ;
      l_TDC_V1190a__ch_low = l_ch * 2 + 1 ;       
      l_TDC_V1190a__buffer [l_TDC_V1190a__ch_high ] = 0xFFFFFFFF ;
      l_TDC_V1190a__buffer [l_TDC_V1190a__ch_low] = 0xFFFFFFFF ;
     }
   
     l_TDC_V1190a__buffer_h = 0 ;
// check for data in buffer
          
// printf (" databuffer 0x%x \n ", *ps_TDC_V767__stat_reg_1[l_mod]);
//  fflush(stdout);
         if ((*ps_TDC_V1190a__stat_reg_1 & 0x0001)==1)
	 {

// printf (" databuffer Event start \n ");
// fflush(stdout);

// if data then read header
//            l_TDC_V1190a__buffer_h  = *pl_TDC_V1190a__outp_buffer;

	
//            l_TDC_V1190a__header = l_TDC_V1190a__buffer_h ;          
//            l_dummy = 0;
//   	   printf ("\n ---------------------\n \n");

//	    if (((l_TDC_V1190a__buffer_h >> 21 )& 3 ) == 2) 
//            {
//   	     printf ("Header found \n");
//	     printf ("Header: %x   Eventno :  %d \n",l_TDC_V1190a__buffer_h ,l_TDC_V1190a__buffer_h&0x00000fff) ;
//	     fflush(stdout);  
//            }

            l_dummy = 0 ;

	    
	    do
	    {
	    
	      l_TDC_V1190a__buffer_h  = *pl_TDC_V1190a__outp_buffer; 
	      
	      
	     // if global header then do nothing
             if (((l_TDC_V1190a__buffer_h >> 27) & 0x1f ) == 0x08 ) 
   		 	  {
				;
			  }

	    
// loop over all hits of this event
             if (((l_TDC_V1190a__buffer_h >> 27) & 0x1f ) == 0x00) 
               {      
		l_ch =  ((l_TDC_V1190a__buffer_h & 0x03f80000)>> 19) ;
		l_TDC_V1190a__ch_low = (l_ch *2 +1) ;
                l_TDC_V1190a__ch_high = (l_ch *2 ) ; 
                l_TDC_V1190a__val_low = ((l_TDC_V1190a__buffer_h & 0x0000ffff)<<16) + l_TDC_V1190a__ch_low ;
                l_TDC_V1190a__val_high = (l_TDC_V1190a__buffer_h & 0x00070000)+ l_TDC_V1190a__ch_high ;
		l_TDC_V1190a__buffer[l_TDC_V1190a__ch_low ] = l_TDC_V1190a__val_low  ;
                l_TDC_V1190a__buffer[l_TDC_V1190a__ch_high]= l_TDC_V1190a__val_high ;
		
		l_dummy++;
	       }           

	       
	       
	       //       printf ("Ch: %x   Time: %x  Eventdata :   %x   \n" ,(l_TDC_V1190a__buffer_h &0x7f000000)>>24,      (l_TDC_V1190a__buffer_h &0x000fffff),l_TDC_V1190a__buffer_h) ; 
//       fflush(stdout);
 
//         if (((l_TDC_V1190a__buffer_h >> 21 )& 0x0003 ) == 0x0) 
//         {
//	   printf (" dataset found \n");
//	   fflush(stdout);
//         }
 
         
	
// if global trailer then do nothing			   
			   
              if (((l_TDC_V1190a__buffer_h >> 27) & 0x1f ) == 0x10 ) 
   		 	  {
			   ;	
			  }
		   
			   
             }
            while (((l_TDC_V1190a__buffer_h >> 27 )& 0x1f ) != 0x10) ;

// check for buffer empty after readout

            if (l_dummy==0 )
             {
               printf ("Event No %d   Empty event in TDC V1190a or data structure error \n ", l_event_counter);
             }
      
	      
	
            if ((*ps_TDC_V1190a__stat_reg_1 & 0x00000001)==1)
             { 
              printf ("Pileup: TDC 1190a buffer not empty after readout! Reseting buffer. \n\n"); 
          
              *ps_TDC_V1190a__sw_clr = 0; 
             } 
         
         // printf ( "\n End of event \n " );
//         *ps_TDC_V1190a__sw_clr = 0;  
          
	    
// check for buffer empty after readout
            if (l_dummy>0)
	    {
	     for (l_ch=0; l_ch<TDC_V1190a__No_Ch; l_ch++)
              {
		l_TDC_V1190a__ch_low = (l_ch *2 +1) ;
                l_TDC_V1190a__ch_high = (l_ch *2 ) ; 
               if (l_TDC_V1190a__buffer [l_TDC_V1190a__ch_low] != 0xFFFFFFFF) 
	       {
		*pl_dat++ = l_TDC_V1190a__buffer [l_TDC_V1190a__ch_high] + TDC_V1190a__lmd_offset  ;
	        *l_se_read_len += 4;
		*pl_dat++ = l_TDC_V1190a__buffer [l_TDC_V1190a__ch_low] + TDC_V1190a__lmd_offset ;
	        *l_se_read_len += 4;
	       }
              } 
	    }
	       
           }
    }
        
    break;
   }  

  }
  break;
  default:
  break;
 }

 return (1);
}

/*****************************************************************************/