CRATE("Master")
{
	GSI_VULOM(0x05000000) {
		trlo2_master = true
	}
	MESYTEC_MADC32(0x00A10000) {
		  nim_busy = gate0
   	          range = 10 V
		  resolution=8
		  hires=true
	}
	BARRIER
	MESYTEC_MADC32(0x00A20000) {
	          nim_busy = gate0
		  range = 10 V
		  resolution=8
		  hires=true
	}
	BARRIER
	CAEN_V775 (0x00C10000) {
		  common_start = false
		  time_range = 1200 ns
		  suppress_invalid = true
		  suppress_over_range = true
	}
	BARRIER
	CAEN_V775 (0x00C20000) {
		  common_start = false
		  time_range = 1200 ns
		  suppress_invalid = true
		  suppress_over_range = true
	}
	BARRIER
        CAEN_V830 (0x00E10000) {
		  resolution = 32	
        }
	BARRIER
	CAEN_V830 (0x00E20000) {
		  resolution = 32
	}
}