Detector: DSSD
Source: CAEN Detector Emulator

Start time: 20:24:14 - 15.05.2021
Stop time:  21:01:34 - 15.05.2021

file name: e127b_run0045.lmd
avrg. rate: 1000Hz
dead-time:  7.5%


Si bias test cycle:
0V > 50V/200uA > 100V/280uA > 150V/370uA > 120V/320uA > 90V/260uA > 60V/210uA > 30V/160uA > 0V
This cycle is run twice i the first 15 minutes and shall be used for calibration of the scaler channels.

Also ESR trafo is running with beam.