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  proton-capture on 118Te  Not logged in ELOG logo
Message ID: 71     Entry time: Fri Mar 20 04:29:45 2020
Author: Jan 
Category: DAQ 
Subject: DAQ settings for the first night 
Year:  
Attachment 1: e127.trlo  7 kB  | Hide | Hide all | Show all
// -*- C++ -*-

/// ************************
// SETUP FILE FOR
// E127 experiment at ESR 2020
/// ************************
/////////////////////////////////
// ADC GATES
si_stretch = 2000 ns;
si_delay = 0 ns;
target_stretch = 15000 ns;
target_delay = 5000 ns; //5000 ns;
master_delay = 800 ns;
//////////////////////////////////
/// DOWNSCALING by 2^n
// n=5 >>  32
// n=6 >>  64
// n=7 >> 128
// n=8 >> 256
// n=9 >> 512
// TARGET ON
si_red   = 0;
xray_red = 0;
baf_red  = 5;//5; 
// TARGET OFF
si_red_OFF   = 0;
xray_red_OFF = 0;
baf_red_OFF  = 0;//5;
//////////////////////////////////
// INPUTS
si_y	=	ECL_IN(1);
si_x	=	ECL_IN(2);

xray1	=	ECL_IN(3);
xray2	=	ECL_IN(4);
xray3	=	ECL_IN(5);

baf	=	ECL_IN(6);
// =       ECL_IN(7);
// =       ECL_IN(8);
// =       ECL_IN(9);
// =       ECL_IN(10);
// =       ECL_IN(11);

trafo   =       ECL_IN(12);
I_cool  =       ECL_IN(13);
U_cool  =       ECL_IN(14);
jet_S1  =       ECL_IN(15);

// =       ECL_IN(16);

jet_on	=	LEMO_IN(1);
jet_off =  	LEMO_IN(2);

//////////////////////////////
// OUTPUTS
si_gate =     GATE_DELAY(1);
target_gate =   GATE_DELAY(3);
qdc_gate  =   GATE_DELAY(4);
master_trig = GATE_DELAY(2);

pico_a = si_gate;
pico_b = target_gate;
//////////////////////////////
// CONSTANTS
long_gate = 2000 ns;
short_gate = 650 ns;

SECTION(all)
{
	FRONT_LED(1) = TRIMI_TDT;

	SERIAL_TSTAMP_IN = SERIAL_TSTAMP_OUT;
	SERIAL_TSTAMP_LATCH = ACCEPT_PULSE;
	slew_counter_add = 0x1000000;

        fast_busy_len = 1000 ns; 
	DEADTIME_IN(1) = TRIMI_TDT;

	/////////////////////////////////////////////////////////////
	//PULSER
        
	// mega_clock
	period(4) = 1 us;   // needed by UDP reader 

	// TRIGGER 11 >> interval for scaler readouts 
	period(1) = 1000 ms;
	
	/////////////////////////////////////////////////////////////
	// TRIGGERS

	// coinc window length
	accept_window_len = 1950 ns;

	// THESE ARE THE VULOM INPUTS (det. triggers)
	// STRETCH THE TRIGGER SIGNAL LONGER THAN THE accept_window_len

	lmu_restart_mode(1) = LEAD_IF_INACT | GATE_ENABLE;
	lmu_stretch(1) = long_gate; // front-back coinc gate

	trig_stretch(1)  = long_gate;
	trig_stretch(2)  = long_gate;
	trig_stretch(3)  = long_gate;

	trig_stretch(9)  = long_gate;
	trig_stretch(10) = long_gate;
	trig_stretch(11) = long_gate;
	
	// SET UP DELAYS TO MATCH THE TRIGGER SIGNALS
	//trig_delay(1) = 800 ns;
	//trig_delay(2) = 800 ns;
	//trig_delay(3) = 1120 ns;

	//trig_delay(9) = 800 ns;
	//trig_delay(10) = 800 ns;
	//trig_delay(11) = 800 ns;
	
	// STANDARD IS MODE_LEADING_EDGE (trigger on the falling edge)
	// MODE_WHEN_PRESENT: check, if a signal is on (e.g. SPILL ON)

	//trig_delay_mode(1) = MODE_THIS | MODE_LEADING_EDGE; 
	
	// DOWNSCALING FACTORS
	// THIS IS FOR GENERATED TPATS (so downscale tpat number with red==2^n)

	trig_red(1) = si_red;
	trig_red(2) = xray_red;
	trig_red(3) = baf_red;

    
	trig_red(9) = si_red_OFF;	
	trig_red(10) = xray_red_OFF;	
	trig_red(11) = baf_red_OFF;	
	
	// ONLY NEEDED FOR MULTI-EVENT MODE / NO NEED NOW
	//multi_trigger = 1;

	////////////////////////////////////////////////////
	// LMU SETUP
	
	// THIS IS THE LOGIC MATRIX.
	// TRIG_LMU_OUT(n) with 'n' being the tpat.

        // TRIG_LMU_AUX 1
        // silicon x/y OR 
	LMU_IN(1) = si_x;
	LMU_IN(2) = si_y;
	LMU_OUT(1) = LMU_IN(1) or LMU_IN(2);
	TRIG_LMU_AUX(1) = LMU_OUT(1);
		
	// TRIG_LMU_AUX 2
        // xray OR
	all_or_mask(2) = xray1 | xray2 | xray3;
	LMU_IN(3) = ALL_OR(2);
	LMU_OUT(2) = LMU_IN(3);
	TRIG_LMU_AUX(2) = ALL_OR(2);

	// TRIG_LMU 3 
	// BaF OR
	LMU_IN(4) = baf;
	LMU_OUT(4) = LMU_IN(4);
	// BaF single
       	TRIG_LMU_AUX(3) = LMU_OUT(4);

	//
	TRIG_PENDING[11] = PULSER(1);

	// TARGET_ON flag is TRIG_LMU_AUX(4)

	// TARGET_ON_TRIGGERS
	TRIG_LMU_OUT(1) = TRIG_LMU_AUX(1) and TRIG_LMU_AUX(4); //Si_ON  
	TRIG_LMU_OUT(2) = TRIG_LMU_AUX(2) and TRIG_LMU_AUX(4); //Xray_ON
	TRIG_LMU_OUT(3) = TRIG_LMU_AUX(3) and TRIG_LMU_AUX(4); //BaF_ON
	TRIG_LMU_OUT(4) = TRIG_LMU_AUX(1) and TRIG_LMU_AUX(3) and TRIG_LMU_AUX(4); //BaF+Si_ON
	//TRIG_LMU_OUT(4) = ;
	//TRIG_LMU_OUT(5) = ;
	//TRIG_LMU_OUT(6) = ;
	//TRIG_LMU_OUT(7) = ;
	//TRIG_LMU_OUT(8) = ;

	// TARGET_OFF_TRIGGERS
	TRIG_LMU_OUT(9)  = TRIG_LMU_AUX(1) and not TRIG_LMU_AUX(4); //Si_OFF
	TRIG_LMU_OUT(10) = TRIG_LMU_AUX(2) and not TRIG_LMU_AUX(4); //Xray_OFF
	TRIG_LMU_OUT(11) = TRIG_LMU_AUX(3) and not TRIG_LMU_AUX(4); //BaF_OFF
	//TRIG_LMU_OUT(12) = ;
	//TRIG_LMU_OUT(13) = ;
	//TRIG_LMU_OUT(14) = ;
	//TRIG_LMU_OUT(15) = ;
	TRIG_LMU_OUT(16) =
	  si_x and si_y and
	  xray1 and xray2 and xray3 and baf and
	  trafo and I_cool and U_cool and jet_S1;
	
	////////////////////////////////////////////////////////////
	// TPAT SETUP
	
	// THIS IS FOR MATCHING: TPAT -> MBS_TRIGGER
	// tpat_trig(n) = m
	// with n = tpat, m = MBS_trigger

        // MBS trigger 1 = JET_ON
	tpat_trig(1) = 1;
	tpat_trig(2) = 1;
	tpat_trig(3) = 1;
	tpat_trig(4) = 1;
	tpat_trig(5) = 1;
	tpat_trig(6) = 1;
	tpat_trig(7) = 1;
	tpat_trig(8) = 1;

	// MBS_trigger 2 = JET_OFF
	tpat_trig(9)  = 2;
	tpat_trig(10) = 2;
	tpat_trig(11) = 2;
	tpat_trig(12) = 2;
	tpat_trig(13) = 2;
	tpat_trig(14) = 2;
	tpat_trig(15) = 2;
	tpat_trig(16) = 2;
        
	// THIS IS FOR ENABLING THE SINGLE TPATS
	// WITH A MASK, OR THE TPATS, OR RANGES WITH n : m.

	tpat_enable = 1:4, 9:11;	
	//tpat_enable = 9:11;	
	//tpat_enable = mask 0xffff;	

	///////////////////////////////////////////////////////
	// GATE & DELAY (MAX=4)

	
	// SET UP THE GATES AND DELAYS

	// Silicon ADC gate
	// si_gate
        GATE_DELAY(1) = MASTER_START;
        delay(1) = si_delay;
	stretch(1) = si_stretch;

	// Masterstart/trigger
	// master_trig
	GATE_DELAY(2) = MASTER_START;
        delay(2) = master_delay;
        stretch(2) = 200 ns;

	// Xray/BaF ADC gate
	// target_gate
	GATE_DELAY(3) = MASTER_START;
        delay(3) = target_delay;
        stretch(3) = target_stretch;

	//unused
	GATE_DELAY(4) = MASTER_START;
	delay(4) = 0 ns;
	stretch(4) = 200 ns;

	////////////////////////////////////////////////////////
	// SIGNAL I/O
	
	// MAP THE LEMO & ECL OUTS
	
        LEMO_OUT(1) = master_trig;
        LEMO_OUT(2) = master_trig;

	ECL_OUT(1) = si_gate; 
	ECL_OUT(2) = si_gate; 
	ECL_OUT(3) = target_gate;
        ECL_OUT(4) = target_gate;
	ECL_OUT(5) = qdc_gate; 
        ECL_OUT(6) = qdc_gate; 
        ECL_OUT(7) = master_trig; 
        ECL_OUT(8) = master_trig; 

	ECL_OUT(9) = pico_a;
	//ECL_OUT(10) = ;
	ECL_OUT(11) = pico_b;
	//ECL_OUT(12) = ;
	//ECL_OUT(13) = ;
	//ECL_OUT(14) = ;
	//ECL_OUT(15) = TRIG_LMU_OUT(1);
	//ECL_OUT(16) = LMU_OUT(1);


	
/* Generates internal BOS and EOS. */
/*
spill_period_duration = 20000000 us;
spill_on_duration =     12000000 us;

SECTION(bos_eos_generate)
{
	period(3) = spill_period_duration;

	GATE_DELAY(3) = PULSER(3);
	stretch(3) = spill_on_duration;
	delay(3) = 0 ns;

	TRIG_PENDING[12] = PULSER(3);
	GATE_DELAY(4) = GATE_DELAY(3);
	stretch(4) = 50 ns;
	delay(4) = 0 ns;
	restart_mode(4) = TRAILING_EDGE;
	TRIG_PENDING[13] = GATE_DELAY(4);

	TRIG_LMU_AUX(3) = GATE_DELAY(3);
}
*/
/* Listens to BOS and EOS from the accelerator. */

	////////////////////////////////////////////////////
	// JET ON/OFF TRIGGER SETUP
	
        EDGE_GATE_START(1) = jet_on;
        TRIG_PENDING[12] = jet_on;

        EDGE_GATE_STOP(1) = jet_off;
        TRIG_PENDING[13] = jet_off;

        TRIG_LMU_AUX(4) = EDGE_GATE(1);

}
Attachment 2: main.cfg  1017 Bytes  | Hide | Hide all | Show all
#log_level = verbose

CRATE("Master")
{
  event_max = 1
  	BARRIER
  	MESYTEC_MADC32(0x00A10000) {
		  nim_busy = gate0
   	          range = 8 V
		  resolution=8
		  hires=true
	}
	BARRIER
	MESYTEC_MADC32(0x00A20000) {
                  nim_busy = gate0
                  range = 4 V
                  resolution=8
                  hires=true
		  }
	#BARRIER
        #CAEN_V965 (0x00B10000) {
	#	  channel_enable = 0..11
        #}
	BARRIER
	CAEN_V775 (0x00C10000) {
		  common_start = false
		  time_range = 1200 ns
		  suppress_invalid = true
		  suppress_over_range = true
	}
	BARRIER
        CAEN_V775 (0x00C20000) {
                  common_start = false
                  time_range = 1200 ns
                  suppress_invalid = true
                  suppress_over_range = true
        }
	BARRIER
	#CAEN_V830 (0x00E10000) {
	#	  resolution = 32	
	#	  }
	#BARRIER
	#CAEN_V830 (0x00E20000) {
        #          resolution = 32
	#}
	#BARRIER
	GROUP("Timetamp")
	GSI_VULOM(0x05000000) {
		timestamp = true
	}
}
Attachment 3: r3bfuser.cfg  916 Bytes  | Show | Hide all | Show all
Attachment 4: setting.1584673412  5 kB  | Show | Hide all | Show all
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