The limit of the leakage current for all Si pads was increased from 1500 nA to 5000nA and 
leakage current was recorded for different Bias Voltages (32V, 35V, 40V, 45V, 50V, 55V 
and 60V).
Since, I_leakage remains < 3 uA for 60 V, it is decided to increase the Bias Voltage for 
all the Si-pads from 32 V to 60 V.
For DSSD and CsI, bias voltages remains same (-50V and -160V respectively).