Here is a brief description of how to change the VME hardware of an exisiting DAQ system to a new configuration.

Our DAQ folders are located in /lynx/Lynx/esr/usr/litv-exp/

The current DAQ running on a specific rio4 is always located in a subfolder named as the hostname of the rio4, e.g. r4l-58.

If you want to change the DAQ on this rio you have to change the config in this folder. Be aware, that the folder name HAS TO BE THE HOSTNAME, no exeptions are allowed! Because of this the r4l-XX folders are usually softlinks to further folders, that contain different versions of the DAQ. 
In practice this means:

1. copy the current folder (e.g. r4l-58_dev) to a new one (e.g. r4l-58_new) and make sure that the link (r4l-58) is set to your new folder (ln -s /../r4l-58_new /../r4l-58)

2. change the hardware of your VME crate and check all VME addresses

3. edit main.cfg in your new DAQ folder, see the example attached here
   - always have a BARRIER between the modules
   - make sure you get the VME addresses right (MesyTec, CAEN board specialties)
   - the order of the modules in this file from top to bottom is important for the next step!

4. edit your start.sh script and all connected scripts and config-files (trloii_setup.sh, vulom.trlo..., a dedicated entry for vulom-configuration will follow)
   - check if DAQ in running, when triggers are provided

5. set up a new unpacker
   -go to the unpacker directory /u/litv-exp/unpacker/unpackexps/ and copy the old unpacker to a new directory:  
   -> cp -r old_up new_up
   -rename the main .spec file:
   -> cd new_up
   -> mv old_up.spec new_up.spec
   -open the Makefile with editor, search and replace "old_up" by "new_up", try compiling:
   -> make clean
   -> make -j

6. configure the data structure of the unpacker
   -make sure you have all the module spec-files that you need included in "new_up.spec", check nurdlib or Hans Törnqvist/Basti Löher in case you do not have it
   -edit the "main_user_esr.spec" to include all your modules (see example attached)
   -the (geom=0x1) field of each module has to be numbered according to the module order in the main.cfg above, starting from 0x1, some modules require additional things (crate=0)
   -edit the "det_mapping.hh" to assign names and types for each channel (example attached)
   -recompile and check upacker with running data stream from the daq:
   -> make -j
   -> ./new_up --stream=r4l-58 --debug (will print only error events)

CRATE("Master")
{
	GSI_VULOM(0x05000000) {
		trlo2_master = true
	}
	MESYTEC_MADC32(0x00500000) {
#		  nim_busy = gate0
#   	          range = 10 V
#		  resolution=8
#		  hires=true
	}
	BARRIER
	CAEN_V775 (0x00A00000) {
		  common_start = false
		  time_range = 1200 ns
		  suppress_invalid = true
		  suppress_over_range = true
	}
	BARRIER
        CAEN_V830 (0x00E00000) {
		  resolution = 32	
        }
	BARRIER
	MESYTEC_MDPP16SCP (0x00200000) {
	 	  auto_pedestals = false
		  # index 0: ADC resolution -> 0: 16 bit ... 4: 12 bit
		  # index 1: TDC resolution -> 0: 24 ps  ... 5: 781 ps
		  resolution = (0, 0)
		  blt_mode = noblt  

		  # true = first single hit.
		  # false = all hits within window.
		  only_first_hit = false

		  # Monitor settings (outputs are NIM2 and NIM3)
		  # Switch monitor on(1) or off(0)
		  monitor_on = 1
		  # Select monitor channel [0..15]
		  monitor_channel = 0
		  # Select monitor waveform
		  # 0: preamp + trigger out
		  # 1: energy shaped signal + timing filter signal
		  # 2: energy shaped signal x 32 + reconstructed baseline
		  # 3: baseline restored signal + timing filter signal
		  monitor_wave = 0

		  # NIM input options
		  # NIM 0: 0 = Off, 1 = Cbus, 4 = Busy out (full), 8 = data thr, 9 = event thr
		  # NIM 1: always trigger output
		  # NIM 2: 0 = Off, 1 = Trigger 1 In, 2 = Reset In
		  # NIM 3: 0,1 = Off, 2 = Sync In (need to set ts_source to external)
		  # NIM 4: 0 = Off, 1 = Trigger 0 In
		  nim = (1 {5})
		  # ECL input options
		  # ECL 0: 0 = Off, 4 = Busy Out, 8 = data threshold, 9 = event threshold
		  # ECL 1: 0 = Off, 1 = Reset In
		  #      + 0 = Terminated, + 16 = Unterminated
		  # ECL 2: 0 = Off, 1 = Sync In, 2 = Trigger 1 In
		  #      + 0 = Terminated, + 16 = Unterminated
		  # ECL 3: 0 = Off, 1 = Trigger 0 In
		  #      + 0 = Terminated, + 16 = Unterminated
		  ecl = (0 {4})
		  # Window ranges:
		  # time_after_trigger: [-25.56 us .. +25.56 us]
		  # width: [0 .. 25.56 us]
		  GATE {
		  	time_after_trigger = -25ns
			width = 1us
		  }

	}		
}

SIGNAL(	ADC_1, esr.madc[0].data[0],
	ADC_32, esr.madc[0].data[31], DATA32);
SIGNAL( ADC_33, esr.madc[1].data[0],
	ADC_64, esr.madc[1].data[31], DATA32);
SIGNAL(	TDC_1, esr.tdc[0].data[0],
	TDC_32, esr.tdc[0].data[31], DATA12);
SIGNAL( TDC_33, esr.tdc[1].data[0],
	TDC_64, esr.tdc[1].data[31], DATA12);
SIGNAL( SC_1, esr.scaler[0].data[0],
        SC_32, esr.scaler[0].data[31],DATA32);
SIGNAL( SC_33, esr.scaler[1].data[0],
	SC_64, esr.scaler[1].data[31],DATA32);
//SIGNAL(ZERO_SUPPRESS_MULTI(20): MDPP_E1);
//SIGNAL(MDPP_E1, esr.mdpp[0].data[0],
//       MDPP_E16, esr.mdpp[0].data[15],DATA16_OVERFLOW);
//SIGNAL(ZERO_SUPPRESS_MULTI(20): MDPP_T1);
//SIGNAL(MDPP_T1, esr.mdpp[0].data[16],
//       MDPP_T16, esr.mdpp[0].data[31],DATA16_OVERFLOW);
//SIGNAL(ZERO_SUPPRESS_MULTI(20): MDPP_TRIG_1);
//SIGNAL(MDPP_TRIG_1, esr.mdpp[0].data[32],
//       MDPP_TRIG_2, esr.mdpp[0].data[33],DATA16_OVERFLOW);