Nik Kurz has setup an mbs-system for me to run with the new IFC, but it is also compatible to the RIO4 (and other VME CPUs).

The special thing about this setup is, that the VULOM priority encoder is exchanged the the VULOM trloii. Special care about the trloii-config needs to be taken.

To change the VME CPU one has to change 2 files and recompile.
1) setup.usf -> there are setup.usf.ifc and setup.usf.rioXX... the file used (setup.usf) needs to be overwritten by the one with the right extension
2) startup.scom -> same here, the used file (startup.scom) needs to be overwritten by the file with the right extension (startup.scom.ifc)
3) make clean; make


List of supported modules (18.07.2023):

MesyTec VMMR (untested)
MesyTec MDPP16 (tested)
MesyTec MADC32 (tested)
MesyTec MTDC32 (tested)

CAEN V775 TDC (tested)
CAEN V785 ADC (tested)
CAEN V830 Scaler (tested)

VULOM trloii (tested)
VULOM SCA32 (tested)

This entry refers to the MBS template from Nik Kurz found at /esr/usr/litv-exp/MBS/templates/2024_MBS_R2_R4_IFC_v1 or similar.

To find the right VME address for your modules, you need the (1) base address, (2) module space and (3) module offset. You simply add those three hex numbers to get the individual module address.

Example: 
V830[2] is the third V830 in this DAQ and has index 2. 
It has 
(1)=0x7000000 
(2)=0x400000 
(3)=0x20000. 

Added up this yields 
0x07440000

So you have to set 0x0744 on the module.

Details:

(1) the base is ususally 0x0700.0000. You only need the 4 hi bits, i.e. 0x0700. It can be readout in setup.usf, there is a line like this:
-------
LOC_MEM_BASE      = (0xe7000000, 0x0,        0x0,        0x0,-
-------

(2) the module space is the start address of the range foreseen for this kind of module in the template. It is defined in the f_used.c:
-------
#define ADDR_OFF_VMMR     0x10000
#define ADDR_OFF_MDPP     0x100000
#define ADDR_OFF_V775     0x200000
#define ADDR_OFF_V785     0x300000
#define ADDR_OFF_V830     0x400000
#define ADDR_OFF_MADC     0x500000
#define ADDR_OFF_MTDC     0x600000
#define ADDR_OFF_VUL_SCAL 0x1000000
-------

(3) the module offset is an incremental offset from the start address given to modules of higher index than 0. The second module of a type has index 1 and will get the offset once, while the first module 
does not get an offset. The offset along with the number of modules of a kind is defined in the f_user.c:
-------
#define N_VMMR         0
#define VMMR_OFF       0x20000

#define N_MDPP         0
#define MDPP_OFF       0x20000

#define N_V775         0
#define N_V775_CHA     32
#define V775_OFF       0x20000

#define N_V785         0
#define N_V785_CHA     32
#define V785_OFF       0x20000

#define N_V830         1
#define N_V830_CHA     32
#define V830_OFF       0x20000

#define N_MADC         0
#define N_MADC_CHA     32
#define MADC_OFF       0x20000

#define N_MTDC         0
#define N_MTDC_CHA     32
#define MTDC_OFF       0x20000

#define N_VUL_SCAL     0
#define N_VUL_SCAL_CHA 32
#define VUL_SCAL_OFF   0x1000000
-------

• to start MBS, always navigate to the folder containing the f_user.c setup for your hardware
  
• it is recommended to start MBS in a sceen session (see at the bottom)
  
• use MBS scripts to do initialitation "startup.scom", shutdown "shutdown.scom" or file writing "runstart.scom"/"runstop.scom" and other things
  these scripts are simple lists of MBS shell commands, one per row
  they should be in your MBS folder and can be created or adjusted as needed
  

> mbs  

> resl  

> rate

> ratf

[CTRL] + [Z]

mbs> @startup

mbs> sh(ow) ac(quisition)

mbs> sh(ow) f(ile)

mbs> t(ype) e(vent) {X} {-v}

[CTRL] + [Z]

mbs> co(nnect) rfio linuxpc.gsi.de -DISK 

mbs> disc(onnect) rfio 

mbs> op(en) f(ile) /path/to/storage/place/file.lmd -disk 

mbs> op(en) f(ile) /path/to/storage/place/file.lmd -rfio 

mbs> op(en) f(ile) file.lmd -rfio {-auto} 

mbs> op(en) f(ile) file.lmd -rfio {-auto} {first=Y} 

mbs> op(en) f(ile) file.lmd -rfio {-auto} {size=X} 

mbs> cl(ose) f(ile) 

mbs> 

mbs> 

mbs> 

mbs> 

mbs> 

mbs> 

[CTRL] + [Z]

Michael Reese and Nik Kurz implemented the SIS3820 scaler module in MBS to be used with RIO4, IFC and MVLC.

Attached is zipped folder for usage with RIO4/IFC (f_user.c, etc.). 

Below is the email by Michael with some explanation and the config needed to implement the module in MVME for use with the MVLC.

######################################################
############ EMAIL by M.Reese 02.10.2024 #############
######################################################

Hallo Jan,

Das SIS3820 Scaler Modul muss auf Adresse 0x08000000 eingedreht werden.

Das NIM-Signal, das die Scaler "latchen" soll, muss für alle Konfigurationen (RIO4/IFC/MVLC) in "input 1" rein. In dem 8er-LEMO-Block ist das der input unten links.

RIO/IFC
Die modifizierte f_user.c fuer SIS3820 readout mit RIO4 / IFC ist hier:
/daq/usr/mreese/mbsrun/rio4l_mesytec_MADC32_test/f_user.c

MVLC
Für MVLC habe ich zwei Readout-Varianten implementiert, du musst mal schauen welche besser für eure Anwendung passt. 

1) Readout über die "Shadow Register". Die latchen die Counter wenn auf "input 1" ein Signal kommt. Diesen Readout kann man entweder mit Blocktransfer oder mit Single Cycle machen. Im Single Cycle kannst du beliebige Subsets an Register wählen. Im Blocktransfer nur zusammenhängende Register. Hier liegen die Daten ab Adresse 0x800.

2) Readout über FIFO. Es gibt hier eine Bitmaske "copy disable register", über die man bestimmen kann welche Counter nicht in die FIFO geschrieben werden. Da es "copy disable" heißt, bedeutet '0' dass der Counter in die Daten kopiert wird. Die Daten werden aus Adresse 0x800000 gelesen, also andere Adresse als die Shadow Register. Hier muss man aufpassen, dass man beim Blocktransfer immer genau die korrekte Anzahl an Werten liest, die in der "copy disable" Maske eingestellt sind. Ansonsten wird der Readout (aus unbekannten Gründen) sehr langsam. Im Prinzip ist das der schnellste Modus, insbesondere wenn du ein nicht zusammenhängendes Subset von Kanälen im Blocktransfer lesen willst. Aber es ist leider etwas komplizierter.

Wenn du die beiden Textabschnitte unten kopierst wie sie sind, dann bekommst du Variante 2) "MULTI CHANNEL SCALER".
Um umzuschalten "LATCHING SCALER" musst du unter der Zeile "# configure the operation mode register" die Zeile mit "mode of operation 0" nehmen, und im Readout Loop eine der beiden unteren Varianten nehmen (die auf Adresse 0x800 lesen). 

Viele Grüsse,
Michael

----------------
MVME workspace:

event_3_hardware_trigger_type_1 -> Rechtsklick -> Add Module -> 


Type: UserModule_10  , Name: SIS3820 , Address : 0x08000000


---------------
Module Init:


# =====================================================================
# Reset the module
# =====================================================================
write a32 d32 0x400 0x1        # KEY_RESET 
write a32 d32 0x404 0x1        # KEY_SDRAM_FIFO_RESET
write a32 d32 0x000 0xffff0000 # clear all bits in Control/Status Register

# =====================================================================
# Setup for "LATCHING SCALER" mode
#  - disadvantage: this has no channel mask, i.e. only a conscutive cahnnels 
#                  can be read out in block mode (blt)
#                  if an arbitraty subset of channels is needed one has to 
#                  do single cycle readout
#
# or 
# 
# Setup for "MULTI CHANNEL SCALER" mode
#  - advantage: this mode allows to select a subset of channels using a mask register (0x104)
#  - disadvantage: this requires the high address space 0x800000
#
# In both modes, the input 1 on the front panel latches the scaler values
# In both modes, the input 3 in the front panel inhibits the counters (i.e. negative gate for the scalers operation)
# 
# Module front panel LEMO outputs / inputs for this configuration
# =====================================================================
# output 7 (10M) (L/M) output 8     L/M = copy of LNE input in Scaler Mode; Copy-to-SDRAM-in-progress in Multi channel Scaler mode
# output 5 ( * ) (10M) output 6     10M = 10 MHz output clock (20 ns pulse)
#  input 3 (InC) ( * ) input 4      InC = inhibit counting (counters stop countig if this is enabled (NIM-enabled = -0.7 V)
#  input 1 (LNE) ( * ) input 2      LNE = load next event (copies all 32 counters into shadow registers) 
# =====================================================================



                               # configure the operation mode register:
#write a32 d32 0x100 0x00220011 # [30:28] mode of operation 0 : "LATCHING SCALER" mode : counter data is copied to shadow registers on LNE (load next event)
write a32 d32 0x100 0x20220011 # [30:28] mode of operation 2 : "MULTI CHANNEL SCALER" mode : counter data is copied to SDRAM in FIFO emulation mode
                               # [21:20] output mode       2 : ouptut 5 -> LNE pulse , outputs 6+7 -> 10 MHz pulses
                               # [18:16] input mode        2 : input 1 -> external next pulse, input 3 -> inhibit counting 
                               # [13:12] select SDRAM mode 1 : SDRAM (instead of FIFO) allows to read data from address 0x800000 
                               # [ 6: 4] LNE (load next event) is taken from input 1 on front panel 
                               # [    0] celect non clearing mode 0: counters are NOT cleared at LNE

# =====================================================================
# Select the channels (only relevant for "MULTI CHANNEL SCALER" mode)
# USER MUST MAKE SURE THAT NUMBER OF ENABLED CHANNELS MATCHES
# THE NUMBER OF WORDS READ IN BLT READOUT AT ADDRESS 0x800000
# =====================================================================
write a32 d32 0x104 0x00000000 # disable no channels (i.e. copy all 32 channels to SDRAM). Readout should be "blt a32 0x800000 32"
#write a32 d32 0x104 0x0fffffff # disable 28 lower channels (i.e. copy 4 channels [31,30,29,28] to SDRAM). Readout should be "blt a32 0x800000 4"
#write a32 d32 0x104 0xffffffbb # disable all but channels 2 to 6. Readout should be "blt a32 0x800000 2"


# =====================================================================
# Enable the module. 
# Writing any value into this register starts the scaler operation.
# =====================================================================
write a32 d32 0x418 0x1        # KEY_OPERATION_ENABLE register: any write access starts scaler operation


----------------
Readout Loop:


# ==================================================================
# Readout for "MULTI CHANNEL SCALER" mode 
# 
# MAKE SURE THAT THE  NUMBER OF 32-BIT-WORDS MUST MATCH 
# THE SUM OF NON DISABLED BITS IN THE COPY DISABLE REGISTER (0x104) 
# IN MODULE INIT
# ==================================================================
blt a32 0x800000 32

# ==================================================================
# Block Transfer Readout for "LATCHING SCALER" mode
# Read shadow registers (latched counters) with block transfer
# The latching happens on LNE signal (front panel input 1)
# ==================================================================
#blt a32 0x800 32

# ==================================================================
# Single Cycle Readout for "LATCHING SCALER" mode
# Read shadow registers with single cycle
# ==================================================================
#read a32 d32 0x800 
#read a32 d32 0x804 
#read a32 d32 0x808 
#read a32 d32 0x80c 

#read a32 d32 0x810 
#read a32 d32 0x814 
#read a32 d32 0x818 
#read a32 d32 0x81c 

#read a32 d32 0x820 
#read a32 d32 0x824 
#read a32 d32 0x828 
#read a32 d32 0x82c 

#read a32 d32 0x830 
#read a32 d32 0x834 
#read a32 d32 0x838 
#read a32 d32 0x83c 

#read a32 d32 0x840 
#read a32 d32 0x844 
#read a32 d32 0x848 
#read a32 d32 0x84c 

#read a32 d32 0x850 
#read a32 d32 0x854 
#read a32 d32 0x858 
#read a32 d32 0x85c 

#read a32 d32 0x860 
#read a32 d32 0x864 
#read a32 d32 0x868 
#read a32 d32 0x86c 

#read a32 d32 0x870 
#read a32 d32 0x874 
#read a32 d32 0x878 
#read a32 d32 0x87c 

####################################
############ EMAIL END #############
####################################