| ID |
Date |
Author |
Category |
Subject |
|
28
|
Sat Mar 28 04:50:34 2020 |
Ragan | Detectors | MWPC |
Alex and Pierre-Michel applied 1500 V to the anode and adjusted the threshold in Messhute.
x1 signal was small & noisy and rest of the signals were fine. |
| Attachment 1: 4475A53F-48AB-430E-8A22-7D92E5FEACBF.jpeg
|
|
|
29
|
Sat Mar 28 11:00:14 2020 |
Ragan, RuiJiu, Mei, Yuri, Tino | Detectors | Movement of detector |
10:51 am the CsISiPHOS is moved to 65 mm from 60 mm.The spot on the DSSSD is changed by 5 mm which confirms the hit of the beam.
11:05
Detector is moved back to 60 mm. |
| Attachment 1: IMG_20200328_110253.jpg
|
|
| Attachment 2: IMG_20200328_110258.jpg
|
|
|
45
|
Sun Mar 29 09:57:26 2020 |
ruijiu | Detectors | the HV of charged particle detector |
MHV1 MHV2
ch1:1st Sipad 4th
Sipad
ch2:2nd Sipad 6th
Sipad
ch3:3rd Sipad DSSD
ch4:4th Sipad CsI |
| Attachment 1: IMG_20200329_095014.jpg
|
|
|
95
|
Mon Mar 30 13:40:57 2020 |
ruijiu | Detectors | HV of Inner detector |
|
| Attachment 1: IMG_20200330_133909.jpg
|
|
|
96
|
Mon Mar 30 13:41:20 2020 |
ruijiu | Detectors | HV of Inner detector |
|
| Attachment 1: IMG_20200330_133909.jpg
|
|
|
99
|
Mon Mar 30 14:48:02 2020 |
ruijiu and Tino | Detectors | The leakcurrent of SiPad is over the setting limit. |
Because the
leakcurrent of
6 Sipads is
over the
setting limit,
the alarm of
HV module is
sounding.
Ruijiu
increase the
limit to 1500
uA. |
| Attachment 1: Screenshot_20200330-145551.jpg
|
|
| Attachment 2: Screenshot_20200330-145544.jpg
|
|
| Attachment 3: IMG_20200330_144915.jpg
|
|
|
100
|
Mon Mar 30 15:03:58 2020 |
ruijiu Tino, Yuri, Lasoro, Nik and Uli | Detectors | the gas bottle is empty. |
The gas bottle was empty. Tino replaced
the previous old bottle with 50 bar gas left.
Yuri is getting new gas bottles.
Yuri got a new gas bottle. We repalced
the the new gas bottle. There is 200
bar gas left now.
The old gas bottle with 50 bar gas
left was kept inside ESR.
The empty gas bottle was removed from
ESR.
The outlet volve was decreased by 30 degree.
Since the value is almost 0, we can not read the value of outlet volve. |
| Attachment 1: IMG_20200330_152735_mh1585575780057.jpg
|
|
|
101
|
Mon Mar 30 16:25:05 2020 |
ruijiu | Detectors | turn down the HV |
turn down the hv and pull out the detector.
suggest by
Hi everybody,
is there now much more rate on the detectors?
Perhaps it helps to turn down the bias for a while and to take the detectors out of the beam, by pulling the pocket out?
And then see if the leakage current comes down again.
good luck, Thomas
***********************************************
Dr. Thomas Faestermann | Tel: +49-89-2723868
Physik Department E12 |
Techn. Univ. Muenchen | Mob: +49-1626193388 |
|
103
|
Mon Mar 30 20:51:06 2020 |
Ragan | Detectors | Bias Voltage for Si-pads |
The limit of the leakage current for all Si pads was increased from 1500 nA to 5000nA and
leakage current was recorded for different Bias Voltages (32V, 35V, 40V, 45V, 50V, 55V
and 60V).
Since, I_leakage remains < 3 uA for 60 V, it is decided to increase the Bias Voltage for
all the Si-pads from 32 V to 60 V.
For DSSD and CsI, bias voltages remains same (-50V and -160V respectively). |
| Attachment 1: Si_pad_bias-voltage.ods
|
|
111
|
Wed Apr 1 01:02:24 2020 |
ruijiu | Detectors | the detector cable is disconnected. |
|
|
112
|
Wed Apr 1 01:05:36 2020 |
ruijiu | Detectors | detector position fixed at 60 mm |
The detector cable was disconnected . We entered and reconnected the cable. |
| Attachment 1: VID_20200401_010416.mp4
|
|
178
|
Thu Nov 19 09:14:40 2020 |
Jan | Detectors | remote MSCF settings for CsISiPHOS |
Attached is a list of all set values for the 5 MSCF shaper modules.
This was done prior to run0251, which served as a final benchmark for those settings.
See: https://elog.gsi.de/esr/E121/62
And https://elog.gsi.de/esr/E121/104
The det. to MSCF assignment is the following:
MSCF 1: Si-pad 1 + 2 p-side/strips (ch. 1-7 + ch. 9-15)
MSCF 2: Si-pad 3 + 4 p-side/strips (ch. 1-7 + ch. 9-15)
MSCF 3: Si-pad 5 p-side/strips (ch. 1-7)
MSCF 4: Si-pad 6 p-side/strips (ch. 1-7)
MSCF 5: DSSD (ch. 1 - 4); CsI (ch. 7 & 8); Si-pad n-sides (ch. 11 - 16)
Note that only the pre-amplification stage of the MSI-8 amplifiers were used for all channels. |
| Attachment 1: setting.1585477986
|
1585477986
Sun Mar 29 12:33:06 CEST 2020
ringpi:mrcc:mscf1:getGainCommon 15
ringpi:mrcc:mscf1:getShapingTimeCommon 2
ringpi:mrcc:mscf1:getThresholdCommon 244
ringpi:mrcc:mscf1:getPzCommon 100
ringpi:mrcc:mscf2:getGainCommon 15
ringpi:mrcc:mscf2:getShapingTimeCommon 2
ringpi:mrcc:mscf2:getThresholdCommon 244
ringpi:mrcc:mscf2:getPzCommon 100
ringpi:mrcc:mscf3:getGainCommon 15
ringpi:mrcc:mscf3:getShapingTimeCommon 2
ringpi:mrcc:mscf3:getThresholdCommon 244
ringpi:mrcc:mscf3:getPzCommon 100
ringpi:mrcc:mscf4:getGainCommon 15
ringpi:mrcc:mscf4:getShapingTimeCommon 2
ringpi:mrcc:mscf4:getThresholdCommon 244
ringpi:mrcc:mscf4:getPzCommon 100
ringpi:mrcc:mscf5:getGainCommon 5
ringpi:mrcc:mscf5:getShapingTimeCommon 2
ringpi:mrcc:mscf5:getThresholdCommon 150
ringpi:mrcc:mscf5:getPzCommon 100
ringpi:mrcc:mscf1:getGain1 15
ringpi:mrcc:mscf1:getGain2 15
ringpi:mrcc:mscf1:getGain3 15
ringpi:mrcc:mscf1:getGain4 15
ringpi:mrcc:mscf1:getShapingTime1 2
ringpi:mrcc:mscf1:getShapingTime2 2
ringpi:mrcc:mscf1:getShapingTime3 2
ringpi:mrcc:mscf1:getShapingTime4 2
ringpi:mrcc:mscf2:getGain1 15
ringpi:mrcc:mscf2:getGain2 15
ringpi:mrcc:mscf2:getGain3 15
ringpi:mrcc:mscf2:getGain4 15
ringpi:mrcc:mscf2:getShapingTime1 2
ringpi:mrcc:mscf2:getShapingTime2 2
ringpi:mrcc:mscf2:getShapingTime3 2
ringpi:mrcc:mscf2:getShapingTime4 2
ringpi:mrcc:mscf3:getGain1 15
ringpi:mrcc:mscf3:getGain2 15
ringpi:mrcc:mscf3:getGain3 15
ringpi:mrcc:mscf3:getGain4 15
ringpi:mrcc:mscf3:getShapingTime1 2
ringpi:mrcc:mscf3:getShapingTime2 2
ringpi:mrcc:mscf3:getShapingTime3 2
ringpi:mrcc:mscf3:getShapingTime4 2
ringpi:mrcc:mscf4:getGain1 15
ringpi:mrcc:mscf4:getGain2 15
ringpi:mrcc:mscf4:getGain3 0
ringpi:mrcc:mscf4:getGain4 0
ringpi:mrcc:mscf4:getShapingTime1 2
ringpi:mrcc:mscf4:getShapingTime2 2
ringpi:mrcc:mscf4:getShapingTime3 2
ringpi:mrcc:mscf4:getShapingTime4 2
ringpi:mrcc:mscf5:getGain1 8
ringpi:mrcc:mscf5:getGain2 3
ringpi:mrcc:mscf5:getGain3 6
ringpi:mrcc:mscf5:getGain4 6
ringpi:mrcc:mscf5:getShapingTime1 2
ringpi:mrcc:mscf5:getShapingTime2 2
ringpi:mrcc:mscf5:getShapingTime3 2
ringpi:mrcc:mscf5:getShapingTime4 2
ringpi:mrcc:mscf1:getThreshold1 20
ringpi:mrcc:mscf1:getThreshold2 20
ringpi:mrcc:mscf1:getThreshold3 20
ringpi:mrcc:mscf1:getThreshold4 20
ringpi:mrcc:mscf1:getThreshold5 20
ringpi:mrcc:mscf1:getThreshold6 20
ringpi:mrcc:mscf1:getThreshold7 0
ringpi:mrcc:mscf1:getThreshold8 0
ringpi:mrcc:mscf1:getThreshold9 20
ringpi:mrcc:mscf1:getThreshold10 20
ringpi:mrcc:mscf1:getThreshold11 20
ringpi:mrcc:mscf1:getThreshold12 20
ringpi:mrcc:mscf1:getThreshold13 20
ringpi:mrcc:mscf1:getThreshold14 0
ringpi:mrcc:mscf1:getThreshold15 0
ringpi:mrcc:mscf1:getThreshold16 0
ringpi:mrcc:mscf1:getPz1 100
ringpi:mrcc:mscf1:getPz2 100
ringpi:mrcc:mscf1:getPz3 100
ringpi:mrcc:mscf1:getPz4 128
ringpi:mrcc:mscf1:getPz5 100
ringpi:mrcc:mscf1:getPz6 100
ringpi:mrcc:mscf1:getPz7 0
ringpi:mrcc:mscf1:getPz8 0
ringpi:mrcc:mscf1:getPz9 100
ringpi:mrcc:mscf1:getPz10 100
ringpi:mrcc:mscf1:getPz11 100
ringpi:mrcc:mscf1:getPz12 100
ringpi:mrcc:mscf1:getPz13 128
ringpi:mrcc:mscf1:getPz14 0
ringpi:mrcc:mscf1:getPz15 0
ringpi:mrcc:mscf1:getPz16 0
ringpi:mrcc:mscf2:getThreshold1 20
ringpi:mrcc:mscf2:getThreshold2 20
ringpi:mrcc:mscf2:getThreshold3 20
ringpi:mrcc:mscf2:getThreshold4 20
ringpi:mrcc:mscf2:getThreshold5 20
ringpi:mrcc:mscf2:getThreshold6 0
ringpi:mrcc:mscf2:getThreshold7 0
ringpi:mrcc:mscf2:getThreshold8 0
ringpi:mrcc:mscf2:getThreshold9 20
ringpi:mrcc:mscf2:getThreshold10 20
ringpi:mrcc:mscf2:getThreshold11 20
ringpi:mrcc:mscf2:getThreshold12 20
ringpi:mrcc:mscf2:getThreshold13 0
ringpi:mrcc:mscf2:getThreshold14 0
ringpi:mrcc:mscf2:getThreshold15 0
ringpi:mrcc:mscf2:getThreshold16 0
ringpi:mrcc:mscf2:getPz1 128
ringpi:mrcc:mscf2:getPz2 128
ringpi:mrcc:mscf2:getPz3 100
ringpi:mrcc:mscf2:getPz4 128
ringpi:mrcc:mscf2:getPz5 100
ringpi:mrcc:mscf2:getPz6 100
ringpi:mrcc:mscf2:getPz7 0
ringpi:mrcc:mscf2:getPz8 0
ringpi:mrcc:mscf2:getPz9 100
ringpi:mrcc:mscf2:getPz10 100
ringpi:mrcc:mscf2:getPz11 100
ringpi:mrcc:mscf2:getPz12 100
ringpi:mrcc:mscf2:getPz13 0
ringpi:mrcc:mscf2:getPz14 0
ringpi:mrcc:mscf2:getPz15 0
ringpi:mrcc:mscf2:getPz16 0
ringpi:mrcc:mscf3:getThreshold1 20
ringpi:mrcc:mscf3:getThreshold2 20
ringpi:mrcc:mscf3:getThreshold3 20
ringpi:mrcc:mscf3:getThreshold4 20
ringpi:mrcc:mscf3:getThreshold5 20
ringpi:mrcc:mscf3:getThreshold6 0
ringpi:mrcc:mscf3:getThreshold7 0
ringpi:mrcc:mscf3:getThreshold8 0
ringpi:mrcc:mscf3:getThreshold9 20
ringpi:mrcc:mscf3:getThreshold10 20
ringpi:mrcc:mscf3:getThreshold11 20
ringpi:mrcc:mscf3:getThreshold12 20
ringpi:mrcc:mscf3:getThreshold13 0
ringpi:mrcc:mscf3:getThreshold14 0
ringpi:mrcc:mscf3:getThreshold15 0
ringpi:mrcc:mscf3:getThreshold16 0
ringpi:mrcc:mscf3:getPz1 128
ringpi:mrcc:mscf3:getPz2 128
ringpi:mrcc:mscf3:getPz3 128
ringpi:mrcc:mscf3:getPz4 128
ringpi:mrcc:mscf3:getPz5 128
ringpi:mrcc:mscf3:getPz6 0
ringpi:mrcc:mscf3:getPz7 0
ringpi:mrcc:mscf3:getPz8 0
ringpi:mrcc:mscf3:getPz9 128
ringpi:mrcc:mscf3:getPz10 128
ringpi:mrcc:mscf3:getPz11 128
ringpi:mrcc:mscf3:getPz12 128
ringpi:mrcc:mscf3:getPz13 0
ringpi:mrcc:mscf3:getPz14 0
ringpi:mrcc:mscf3:getPz15 0
ringpi:mrcc:mscf3:getPz16 0
ringpi:mrcc:mscf4:getThreshold1 244
ringpi:mrcc:mscf4:getThreshold2 244
ringpi:mrcc:mscf4:getThreshold3 244
ringpi:mrcc:mscf4:getThreshold4 244
ringpi:mrcc:mscf4:getThreshold5 244
ringpi:mrcc:mscf4:getThreshold6 244
ringpi:mrcc:mscf4:getThreshold7 244
ringpi:mrcc:mscf4:getThreshold8 244
ringpi:mrcc:mscf4:getThreshold9 244
ringpi:mrcc:mscf4:getThreshold10 244
ringpi:mrcc:mscf4:getThreshold11 244
ringpi:mrcc:mscf4:getThreshold12 244
ringpi:mrcc:mscf4:getThreshold13 244
ringpi:mrcc:mscf4:getThreshold14 244
ringpi:mrcc:mscf4:getThreshold15 244
ringpi:mrcc:mscf4:getThreshold16 244
ringpi:mrcc:mscf4:getPz1 100
ringpi:mrcc:mscf4:getPz2 100
ringpi:mrcc:mscf4:getPz3 100
ringpi:mrcc:mscf4:getPz4 100
ringpi:mrcc:mscf4:getPz5 100
ringpi:mrcc:mscf4:getPz6 0
ringpi:mrcc:mscf4:getPz7 0
ringpi:mrcc:mscf4:getPz8 0
ringpi:mrcc:mscf4:getPz9 100
ringpi:mrcc:mscf4:getPz10 100
ringpi:mrcc:mscf4:getPz11 100
ringpi:mrcc:mscf4:getPz12 100
ringpi:mrcc:mscf4:getPz13 0
ringpi:mrcc:mscf4:getPz14 0
ringpi:mrcc:mscf4:getPz15 0
ringpi:mrcc:mscf4:getPz16 0
ringpi:mrcc:mscf5:getThreshold1 50
ringpi:mrcc:mscf5:getThreshold2 50
ringpi:mrcc:mscf5:getThreshold3 50
ringpi:mrcc:mscf5:getThreshold4 50
ringpi:mrcc:mscf5:getThreshold5 150
ringpi:mrcc:mscf5:getThreshold6 150
ringpi:mrcc:mscf5:getThreshold7 150
ringpi:mrcc:mscf5:getThreshold8 150
ringpi:mrcc:mscf5:getThreshold9 150
ringpi:mrcc:mscf5:getThreshold10 150
ringpi:mrcc:mscf5:getThreshold11 150
ringpi:mrcc:mscf5:getThreshold12 150
ringpi:mrcc:mscf5:getThreshold13 150
ringpi:mrcc:mscf5:getThreshold14 150
ringpi:mrcc:mscf5:getThreshold15 150
ringpi:mrcc:mscf5:getThreshold16 150
ringpi:mrcc:mscf5:getPz1 100
ringpi:mrcc:mscf5:getPz2 100
ringpi:mrcc:mscf5:getPz3 100
ringpi:mrcc:mscf5:getPz4 100
ringpi:mrcc:mscf5:getPz5 100
ringpi:mrcc:mscf5:getPz6 100
ringpi:mrcc:mscf5:getPz7 100
ringpi:mrcc:mscf5:getPz8 100
ringpi:mrcc:mscf5:getPz9 100
ringpi:mrcc:mscf5:getPz10 100
ringpi:mrcc:mscf5:getPz11 100
ringpi:mrcc:mscf5:getPz12 100
ringpi:mrcc:mscf5:getPz13 100
ringpi:mrcc:mscf5:getPz14 100
ringpi:mrcc:mscf5:getPz15 100
ringpi:mrcc:mscf5:getPz16 100
ringpi:mrcc:mscf1:getSingleChMode 0
ringpi:mrcc:mscf2:getSingleChMode 0
ringpi:mrcc:mscf3:getSingleChMode 0
ringpi:mrcc:mscf4:getSingleChMode 0
ringpi:mrcc:mscf5:getSingleChMode 1
ringpi:mrcc:mscf1:getRcMode 1
ringpi:mrcc:mscf2:getRcMode 1
ringpi:mrcc:mscf3:getRcMode 1
ringpi:mrcc:mscf4:getRcMode 1
ringpi:mrcc:mscf5:getRcMode 1
ringpi:mrcc:mscf1:getAutoPZ 0
ringpi:mrcc:mscf2:getAutoPZ 0
ringpi:mrcc:mscf3:getAutoPZ 0
ringpi:mrcc:mscf4:getAutoPZ 1
ringpi:mrcc:mscf5:getAutoPZ 0
ringpi:mrcc:mscf1:getMultiplicityHi 8
ringpi:mrcc:mscf2:getMultiplicityHi 1
ringpi:mrcc:mscf3:getMultiplicityHi 1
ringpi:mrcc:mscf4:getMultiplicityHi 1
ringpi:mrcc:mscf5:getMultiplicityHi 4
ringpi:mrcc:mscf1:getMultiplicityLo 8
ringpi:mrcc:mscf2:getMultiplicityLo 0
ringpi:mrcc:mscf3:getMultiplicityLo 0
ringpi:mrcc:mscf4:getMultiplicityLo 0
ringpi:mrcc:mscf5:getMultiplicityLo 4
ringpi:mrcc:mscf1:getSumTrgThresh 0
ringpi:mrcc:mscf2:getSumTrgThresh 0
ringpi:mrcc:mscf3:getSumTrgThresh 0
ringpi:mrcc:mscf4:getSumTrgThresh 0
ringpi:mrcc:mscf5:getSumTrgThresh 0
ringpi:mrcc:mscf1:getBlrOn 1
ringpi:mrcc:mscf2:getBlrOn 1
ringpi:mrcc:mscf3:getBlrOn 1
ringpi:mrcc:mscf4:getBlrOn 1
ringpi:mrcc:mscf5:getBlrOn 1
ringpi:mrcc:mscf1:getCoincTime 121
ringpi:mrcc:mscf2:getCoincTime 0
ringpi:mrcc:mscf3:getCoincTime 0
ringpi:mrcc:mscf4:getCoincTime 0
ringpi:mrcc:mscf5:getCoincTime 0
ringpi:mrcc:mscf1:getThreshOffset 0
ringpi:mrcc:mscf2:getThreshOffset 0
ringpi:mrcc:mscf3:getThreshOffset 0
ringpi:mrcc:mscf4:getThreshOffset 0
ringpi:mrcc:mscf5:getThreshOffset 0
ringpi:mrcc:mscf1:getShaperOffset 0
ringpi:mrcc:mscf2:getShaperOffset 0
ringpi:mrcc:mscf3:getShaperOffset 0
ringpi:mrcc:mscf4:getShaperOffset 0
ringpi:mrcc:mscf5:getShaperOffset 0
ringpi:mrcc:mscf1:getBlrThresh 20
ringpi:mrcc:mscf2:getBlrThresh 20
ringpi:mrcc:mscf3:getBlrThresh 25
ringpi:mrcc:mscf4:getBlrThresh 25
ringpi:mrcc:mscf5:getBlrThresh 25
ringpi:mrcc:mscf1:getECLDelay 0
ringpi:mrcc:mscf2:getECLDelay 0
ringpi:mrcc:mscf3:getECLDelay 0
ringpi:mrcc:mscf4:getECLDelay 0
ringpi:mrcc:mscf5:getECLDelay 0
|
| Attachment 2: det_mapping.png
|
|
|
180
|
Tue Dec 8 15:47:07 2020 |
Jan | Detectors | manual preamp & shaper settings for CsISiPhos |
attached is a document showing fotos of all involved amplifiers in the chain to document the manual settings active during the experiment.
Summary:
Si-pad n-sides [MSI-8 (1)] were set to 5 GeV (expected E-deposition ~2 GeV)
Si-pad p-sides [MPR-32 (1 & 2)] were set to 1 GeV (expected E-deposition ~2 GeV)
DSSD channels [MSI-8 (2)] were set to 5 GeV (expected E-deposition ~1.2 GeV)
CsI channels [MSI-8 (2)] were set to 4 GeV (expected E-deposition 46 GeV)
It seems we got clipped signals from the Si-pad p-sides, because the MPR-32 were saturated due to a wrong gain setting.
This might explain, why there was not real influence on the spectra when adjusting MSCF settings for those channels.
I cannot comment on the CsI gain setting, because i don't know whether the given GeV-range by MesyTec directly applies for CsI & photodiode.
However, for DSSD and Si-pad n-sides the settings look okay. |
| Attachment 1: amp_settings.pdf
|
|
|
13
|
Wed Jan 29 10:42:42 2020 |
Shahab | General | Gas target control with the new control system event |
Many thanks to Sergey and Nikos we have tested the connection of the new control system for turning on and off of the gas target.
Connections:
For the test event machines 12 (event 162) and 14 (event 163) were chosen for gas target on and off. The old Pulzzentrale code remains unchanged on 10. The middle output of the TIF editors can then be connected to the gas target control.
The created pulses were measured on the oscilloscope and hat the duration of 1us and amplitude of 5V.
The gas target control then produces the required long pulse which comes out as a BNC connection. If in the local mode, gas target can controlled by out-on and out-off. For the above scenario, we need the event mode.
The output of the gas target control is connected to the ESR-Messhuette-Panel number 2, which goes back to Messhuete and form there to the top of ESR.
All connections are working properly until the gas target itself.
Software:
Different subchains can be activated and deactivated on demand. Also their duration can be changed on the fly, but currently a change in other settings (such as Quadrupoles) might reset the duration values to their default. |
| Attachment 1: IMG_20200128_153508.jpg
|
|
| Attachment 2: IMG_20200128_145345.jpg
|
|
| Attachment 3: IMG_20200128_145340.jpg
|
|
| Attachment 4: IMG_20200128_145307.jpg
|
|
| Attachment 5: IMG_20200128_144555.jpg
|
|
|
14
|
Fri Feb 21 11:30:52 2020 |
Laszlo | General | Shift plan |
e127: https://docs.google.com/spreadsheets/d/14m8WcCq1erx6HqWJRK7TLbCx121IkjqGa5l-frf4YjI/edit#gid=0
e121: https://docs.google.com/spreadsheets/d/10MUzA5-Ilf2WzCyNj8u_KSG6yzPg0e4vtZGGPFB3K-k/edit#gid=0 |
|
18
|
Thu Mar 26 17:21:40 2020 |
Ragan | General | Stochastic cooling |
1) From SIS, 206Pb67+ @401.17 MeV/u goes to FRS where only SEETRAM is placed in the target area to strip off 206Pb67+ to get 206Pb81+.
2) There is 206Pb81+ (H-like primary beam) inside ESR at 400 MeV/u.
3) The ESR team is now trying Stochastic cooling with 206Pb81+ beam at 400 MeV/u. |
|
19
|
Fri Mar 27 13:02:07 2020 |
Ragan | General | Stochastic cooling |
1) ESR team is successful with the Stochstic cooling of primary H-like 206Pb81+ beam @400 MeV/u.
2) Now, they are trying for stacking of the beam. |
| Attachment 1: stochastic_cooling.PNG
|
|
|
20
|
Fri Mar 27 13:04:17 2020 |
Ragan | General | FRS Settings until now |
Yuri and Helmut have been extensively involved in tuning and optimizing of the FRS.
26th March, 2020 (Evening setting):
1) 206Pb67+ beam from SIS @401.17 MeV/u.
2) SEETRAM in target area of FRS is used for stripping the beam from SIS to get 206Pb81+ and is then transported to ESR @400 MeV/u. (SEETRAM consists of three Ti foils of ~10 um thickness which are used for stripping purpose (more info: https://www-win.gsi.de/frs-setup/ ))
3) SL1 slits are opened +-10 mm to get rid of other charge states of 206Pb and only transport 206Pb81+ through FRS.
27th March, 2020 (Evening setting):
1) Different target (Be 1-6 g/cm2 with Nb backing) and degrader (Al)thicknesses are used for the optimization of 206Pb81+ with matter in FRS to get the beam with @400 MeV/u in ESR.
2) 206Pb67+ beam from SIS @540-560 MeV/u. |
| Attachment 1: frs.pdf
|
|
| Attachment 2: FRS.pdf
|
|
|
21
|
Fri Mar 27 13:40:54 2020 |
Ragan | General | NTCap start and shutdown information |
The attachment contains information on how to start and shutdown NTCap and bridge computer. |
| Attachment 1: ntcapmanual.pdf
|
|
|
22
|
Fri Mar 27 19:51:37 2020 |
Ragan | General | ESR Machine |
By changing the tune to Qx=2.33, Qy=2.36 the momentum acceptance was significantly improved. A variation of the cooler voltage of 10300 V was possible without beam loss. That corresponds to a momentum acceptance of 2.7 %. That should provide good conditions for longitudinal stacking.
Thanks to the ESR team ! |